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| 型號(hào)： | OR3T1257PS208-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 186000 GATES, PQFP208 |
| 封裝： | PLASTIC, SQFP2-208 |
| 文件頁(yè)數(shù)： | 122/203頁(yè) |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3T1257PS208-DB |
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Lattice Semiconductor
25
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
PLC Routing Resources
Generally, the ispLEVER Development System is used
to automatically route interconnections. Interactive
routing with the ispLEVER design editor (EPIC) is also
available for design optimization. To use EPIC for inter-
active layout, an understanding of the routing
resources is needed and is provided in this section.
The routing resources consist of switching circuitry and
metal interconnect segments. Generally, the metal
lines which carry the signals are designated as routing
segments. The switching circuitry connects the routing
segments, providing one or more of three basic func-
tions: signal switching, amplication, and isolation. A
net running from a PFU or PIC output (source) to a
PLC or PIC input (destination) consists of one or more
routing segments, connected by switching circuitry
called congurable interconnect points (CIPs).
The following sections discuss PLC, PIC, and interquad
routing resources. This section discusses the PLC
switching circuitry, intra-PLC routing, inter-PLC routing,
and clock distribution.
Configurable Interconnect Points
The process of connecting routing segments uses
three basic types of switching circuits: two types of con-
gurable interconnect points (CIPs) and bidirectional
buffers (BIDIs). The basic element in CIPs is one or
more pass transistors, each controlled by a congura-
tion RAM bit. The two types of CIPs are the mutually
exclusive (or multiplexed) CIP and the independent
CIP.
A mutually exclusive set of CIPs contains two or more
CIPs, only one of which can be on at a time. An inde-
pendent CIP has no such restrictions and can be on
independent of the state of other CIPs. Figure 18
shows an example of both types of CIPs.
Key: C = conguration data.
5-5973(C)
Figure 18. Configurable Interconnect Point
3-Statable Bidirectional Buffers
Bidirectional buffers, previously described in the SLIC
section of the programmable logic cell discussion, pro-
vide isolation as well as amplication for signals routed
a long distance. Bidirectional buffers are also used to
route signals diagonally in the PLC (described later in
the subsection entitled Intra-PLC Routing), and BIDIs
can be used to indirectly route signals through the
switching routing (xSW) segments. Any number from
zero to ten BIDIs can be used in a given PLC.
MULTIPLEXED CIP
A
B
C
O
A
B
C
O
CD
INDEPENDENT CIP
A
B
CD
B
A
=
2
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| OR3T125-7PS208I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-7PS240 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1257PS240-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-7PS240I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T20 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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