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參數(shù)資料
| 型號： | OR3T1256PS240I-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| 封裝： | PLASTIC, SQFP2-240 |
| 文件頁數(shù)： | 160/203頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | OR3T1256PS240I-DB |
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6
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Description (continued)
PIC Logic
Series 3 PIC addresses the demand for ever-increas-
ing system clock speeds. Each PIC contains four pro-
grammable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fast-
capture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a sys-
tem clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the
ORCA 2C/2T capability to use any input
pin as a clock or other global input is maintained.
On the output side of each PIO, two outputs from the
PLC array can be routed to each output ip-op, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals.
The output FF in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is very similar to the
ORCA 2C/2T Series buffer with a new, fast, open-drain
option for ease of use on system buses.
System Features
Series 3 also provides system-level functionality by
means of its dual-use microprocessor interface and its
innovative programmable clock manager. These func-
tional blocks allow for easy glueless system interfacing
and the capability to adjust to varying conditions in
today’s high-speed systems.
Routing
The abundant routing resources of the
ORCA Series 3
FPGAs are organized to route signals individually or as
buses with related control signals. Clocks are routed on
a low-skew, high-speed distribution network and may
be sourced from PLC logic, externally from any I/O
pad, or from the very fast ExpressCLK pins. Express-
CLKs may be glitchlessly and independently enabled
and disabled with a programmable control signal using
the new StopCLK feature. The improved PIC routing
resources are now similar to the patented intra-PLC
routing resources and provide great exibility in moving
signals to and from the PIOs. This exibility translates
into an improved capability to route designs at the
required speeds when the I/O signals have been
locked to specic pins.
Conguration
The FPGA’s functionality is determined by internal
conguration RAM. The FPGA’s internal initialization/
conguration circuitry loads the conguration data at
powerup or under system control. The RAM is loaded
by using one of several conguration modes. The con-
guration data resides externally in an EEPROM or any
other storage media. Serial EEPROMs provide a sim-
ple, low pin count method for conguring FPGAs. A
new, easy method for conguring the devices is
through the microprocessor interface.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-7BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1257BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-7BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-7BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1257BC432-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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