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| 型號(hào)： | OR3T1256PS240I-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 186000 GATES, PQFP240 |
| 封裝： | PLASTIC, SQFP2-240 |
| 文件頁(yè)數(shù)： | 124/203頁(yè) |
| 文件大小： | 1368K |
| 代理商： | OR3T1256PS240I-DB |
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Lattice Semiconductor
27
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Intra-PLC Routing
The function of the intra-PLC routing resources is to
connect the PFU’s input and output ports to the routing
resources used for entry to and exit from the PLC. This
routing provides PFU feedback, corner turning, or
switching from one type of routing resource to another.
Flexible Input Structure (FINS)
The exible input switching structure (FINS) in each
PLC of the
ORCA Series 3 provides for the exibility of
a crossbar switch from the routing resources to the
PFU inputs while taking advantage of the routability of
shared inputs. Connectivity between the PLC routing
resources and the PFU inputs is provided in two
stages. The primary FINS switch has 50 inputs that
connect the PLC routing to the 35 inputs on the sec-
ondary switch. The outputs of the second switch con-
nect to the 50 PFU inputs. The switches are
implemented to provide connectivity for bused signals
and individual connections.
PFU Output Switching
The PFU outputs are switched onto PLC routing
resources via the PFU output multiplexer (OMUX). The
PFU output switching segments from the output multi-
plexer provide ten connections to the PLC routing out
of 18 possible PFU outputs (F[7:0], Q[7:0], DOUT,
REGCOUT). These output switching segments connect
segment for segment to the SUR, SUL, SLR, and SLL
switching segments described below (e.g., O4 con-
nects only to SUR4, not SUR5). The output switching
segments also feed directly into the SLIC on a seg-
ment-by-segment basis. This connectivity is also
described below.
Switching Routing Segments (xSW)
There are four sets of switching routing segments in
each PLC. Each set consists of ten switching elements:
SUL[9:0], SUR[9:0], SLL[9:0], and SLR[9:0], tradition-
ally labeled for the upper-left, upper-right, lower-left,
and lower-right sections of the PFUs, respectively. The
xSW routing segments connect to the PFU inputs and
outputs as well as the BIDI routing segments, to be
described later. They also connect to both the horizon-
tal and vertical x1 and x5 routing segments (inter-PLC
routing resources, described later) in their specic cor-
ner. xSW segments can be used for fast connections
between adjacent PLCs or PICs without requiring the
use of inter-PLC routing resources. This capability not
only increases signal speed on adjacent PLC routing,
but also reduces routing congestion on the principal
inter-PLC routing resources. The SLL and SUR seg-
ments combine to provide connectivity to the PLCs to
the left and right of the current PLC; the SLR and SUL
segments combine to provide connectivity to the PLCs
above and below the current PLC.
Fast routes on switching segments to diagonally adja-
cent PLCs/PICs are possible using the BIDI routing
segments (discussed below) and the SLL and SLR
switching segments. The BR BIDI routing segments
combine with the SUL switching segments of the PLC
below and to the right of the current PLC to connect to
that PLC. The BL BIDI routing segments combine with
the SLL switching segments of the PLC above and to
the right of the current PLC to connect to that PLC.
These fast diagonal connections provide a great
amount of exibility in routing congested areas of logic
and in shifting data on a per-PLC basis such as per-
forming implicit multiplications/divisions in routing
between functional logic elements.
Switching routing segments are also the chief means
by which signals are transferred between the inter-PLC
routing resources and the PFU. Each set of switching
segments has connectivity to the x1 routing segments,
and there is varying connectivity to the x5, xH, and xL
inter-PLC routing segments. Detailed information on
switching segment/inter-PLC routing connectivity is
provided later in this section in the Inter-PLC Routing
Resources subsection.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-7BA352 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1257BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125-7BA352I | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-7BC432 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T1257BC432-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 6272 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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