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參數(shù)資料
| 型號： | OR3T125-4B432 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
| 封裝： | BGA-432 |
| 文件頁數(shù)： | 1/210頁 |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3T125-4B432 |
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ORCA Series 3
Field-Programmable Gate Arrays
Preliminary Data Sheet, Rev. 1
September 1998
Features
T High-performance, cost-effective, 0.35 m (OR3C) and
0.3 m (OR3T) 4-level metal technology, with a migra-
tion plan to 0.25 m technology (4- or 5-input look-up
table delay of 1.7 ns with -5 speed grade in 0.35 m).
T Up to 186,000 usable gates in 0.3 m, expanding to
320,000 usable gates in 0.25 m.
T Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
T Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
T New twin-quad programmable function unit (PFU) archi-
tecture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
T Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be dis-
abled per PFU.
T New flexible input structure (FINS) of the PFUs provides
a routability enhancement for LUTs with shared inputs
and the logic flexibility of LUTs with independent inputs.
T Fast-carry logic and routing to adjacent PFUs for
nibble-, byte-wide, or longer arithmetic functions, with
the new option to register the PFU carry-out.
T New softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
T New supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder, and
PAL*-like AND-OR with optional INVERT in each pro-
grammable logic cell (PLC).
T Abundant hierarchical routing resources based on rout-
ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
ing delay.
T TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
T Individually programmable drive capability: 12 mA sink/
6 mA source or 6 mA sink/3 mA source.
T Built-in boundary scan (IEEE
1149.1 JTAG) and
3-state all I/O pins (TS_ALL) testability functions.
T Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
T Up to four new ExpressCLK inputs allow extremely fast
clocking of signals on- and off-chip plus access to inter-
nal general clock routing.
T New StopCLK feature to glitchlessly stop/start Express-
CLK
s independently by user command.
T New programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF)
latch for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and
PAL-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
*
PAL is a trademark of Advanced Micro Devices, Inc.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCA Series 3 FPGAs
The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
Device
Usable Gates
Max
Registers
Max User
RAM Bits
Max
User I/Os
Array Size
OR3T20
18K—36K
1872
18K
192
12 x 12
OR3T30
24K—48K
2436
25K
224
14 x 14
OR3C/T55
40K—80K
3780
41K
288
18 x 18
OR3C/T80
58K—116K
5412
62K
352
22 x 22
OR3T125
92K—186K
8400
100K
448
28 x 28
OR3T165
120K—244K
10752
131K
512
32 x 32
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T125-4B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
| OR3T125-4BA352I | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| OR3T125-4BA352 | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| OR3T125-5B432 | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
| OR3T125-5B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4PS208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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