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參數(shù)資料
| 型號： | OR3LP26B |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable System Chip，Embedded Master/Target PCI Bus Interface(現(xiàn)場可編程系統(tǒng)芯片，嵌入式主機/從機PCI總線接口) |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片，嵌入式主/ PCI總線目標接口（現(xiàn)場可編程系統(tǒng)芯片，嵌入式主機/從機的PCI總線接口） |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 151K |
| 代理商： | OR3LP26B |
4
Lucent Technologies Inc.
Preliminary Product Brief
September 1999
Embedded Master/Target PCI Bus Interface
ORCA OR3LP26B FPSC
FPSC Highlights
(continued)
— 32 x 4
RAM per PFU, configurable as single or
dual port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Built-in boundary scan (IEEE* 1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
I
High-speed, 64-bit
on-chip interface provided
between FPGA logic and embedded core to reduce
bottlenecks typically found when interfacing off-chip.
I
Supported in four packages: 240-pin SQFP2,
352-pin PBGA, 432-pin EBGA, 680-pin EBGA (64-bit
PCI not offered in 240-pin package).
I
Pin-selectable I/O clamping diodes to allow either
3.3 V input clamp or 5 V tolerance on FPGA side
inputs.
Software Support
I
Supported by ORCA Foundry software and third-
party CAE tools for implementing ORCA Series 3+
devices and simulation/timing analysis with embed-
ded PCI bus core.
I
PCI core configuration options and simulation netlists
generated by FPSC configuration manager utility in
ORCAFoundry software.
I
Preference files provided for timing interface between
PCI bus core and FPGA logic.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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