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參數(shù)資料
| 型號(hào)： | OR3LP26B |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable System Chip，Embedded Master/Target PCI Bus Interface(現(xiàn)場(chǎng)可編程系統(tǒng)芯片，嵌入式主機(jī)/從機(jī)PCI總線接口) |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片，嵌入式主/ PCI總線目標(biāo)接口（現(xiàn)場(chǎng)可編程系統(tǒng)芯片，嵌入式主機(jī)/從機(jī)的PCI總線接口） |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 151K |
| 代理商： | OR3LP26B |
2
Lucent Technologies Inc.
Preliminary Product Brief
September 1999
Embedded Master/Target PCI Bus Interface
ORCA OR3LP26B FPSC
PCI Bus Core Highlights
(continued)
I
FPGA is reconfigurable via the PCI interface's config-
uration space (as well as conventionally), allowing
the FPGA to be field-updated to meet late-breaking
requirements or emerging protocols.
I
Master:
— Generates all defined command codes except
interrupt acknowledge and special cycle.
— Capable of accessing its own local Target in con-
figuration, memory, and I/O space.
— Capable of acting as the system's configuration
agent by booting up with the Master logic
enabled.
— Supports multiple options for Master bus requests,
to increase PCI bus bandwidth.
— Supports single-cycle I/O space accesses.
— Provides option to delay PCI access until FIFO is
full on Master writes to increase PCI bandwidth.
— Supports programmable latency timer control.
I
Target:
— Responds legally to all command codes: Interrupt
acknowledge, special cycle, and reserved com-
mands ignored; memory read multiple and line
handled as memory read; memory write and
invalidate handled as memory write.
— Implements target abort, disconnect, retry, and
wait cycles.
— Handles delayed transactions.
— Handles fast back-to-back transactions.
— Method of handling retries is programmable at
FPGA configuration to allow tailoring to different
Target data access latencies.
— Decodes at medium speed.
— Provides option to delay PCI access until FIFO is
full on Target reads to increase PCI bandwidth.
I
Supports dual-address cycles (both as Master and
Target).
I
Supports all six base address registers (BARs), as
either memory (32-bit or 64-bit) or I/O. Any legal
page size can be independently specified for each
BAR during FPGA configuration.
I
Independent Master and Target clocks can be sup-
plied to the PCI FIFO interface from the FPGA-based
logic.
I
Provides versatile clocking capabilities with FPGA
clocks sourced from PCI bus clock or elsewhere.
FIFO interface buffers asynchronous clock domains
between the PCI interface and FPGA-based logic.
I
PCI interface timing: meets or exceeds 33 MHz,
50 MHz, and 66 MHz PCI requirements.
I
Configuration options set during FPGA configuration:
— Class code, revision ID.
— Latency timer.
— Cache line size.
— Subsystem ID.
— Subsystem vendor ID.
— Maximum latency, minimum grant.
— Interrupt line.
— Hot Plug/Hot Swap capability.
I
Generates interrupts on INTA# as directed by the
FPGA.
I
PCI I/O output drivers can be programmed for fast or
slew-limited operation; both are PCI compliant.
I
Ideally suited for such applications as:
— PCI-based graphics/video/multimedia.
— Bridges to ISA/EISA/MCA, LAN, SCSI, Ethernet,
ATM, or other bus architectures.
— High-bandwidth data transfer in proprietary sys-
tems.
Parameter
33 MHz
11.0 ns
7.0 ns
10.0 ns
2.0 ns
30.0 ns
50 pF
50 MHz
7.5 ns
4.5 ns
6.5 ns
1.5 ns
20.0 ns
50 pF
66 MHz
6.0 ns
3.0 ns
5.0 ns
1.0 ns
15.0 ns
10 pF
Device Clock => Out
Device Setup Time
Board Prop. Delay
BoArd Clock Skew
Total Budget
Load Capacitance
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