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參數(shù)資料
| 型號(hào)： | OR3LP26B |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable System Chip，Embedded Master/Target PCI Bus Interface(現(xiàn)場(chǎng)可編程系統(tǒng)芯片，嵌入式主機(jī)/從機(jī)PCI總線接口) |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片，嵌入式主/ PCI總線目標(biāo)接口（現(xiàn)場(chǎng)可編程系統(tǒng)芯片，嵌入式主機(jī)/從機(jī)的PCI總線接口） |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 151K |
| 代理商： | OR3LP26B |
Preliminary Product Brief
September 1999
Lucent Technologies Inc.
3
Embedded Master/Target PCI Bus Interface
ORCA OR3LP26B FPSC
PCI Bus Core Highlights
(continued)
5-6368(F).e
Figure 1. ORCA OR3LP26B PCI FPSC Block Diagram
113 USER I/O PADS
OR3T SERIES FPGA
18 ROWS x 28 COLUMNS
73
USER
I/O PADS
73
USER
I/O PADS
PCI
MASTER/TARGET
INTERFACE
PCI
BUS
DATA CONTROL
AND
MULTIPLEXING
32
32
32
32
16 DEEP
FIFO
64-bit x
16 DEEP
FIFO
64-bit x
32 DEEP
FIFO
64-bit x
32 DEEP
FIFO
64-bit x
113 USER I/O PADS
OR3T SERIES FPGA
18 ROWS x 28 COLUMNS
73
USER
I/O PADS
73
USER
I/O PADS
32 DEEP
FIFO
PCI
MASTER/TARGET
INTERFACE
PCI
BUS
DATA CONTROL
AND
MULTIPLEXING
64
64
64-bit x
32 DEEP
FIFO
64-bit x
16 DEEP
FIFO
64-bit x
16 DEEP
FIFO
64-bit x
FPSC Highlights
I
Implemented as an embedded core into the
advanced ORCA Series 3+ FPSC architecture.
I
Allows the user to integrate the core with up to 120K
gates of programmable logic, all in one device, and
provides up to 259 user I/O pins in addition to the
PCI interface pins.
I
FPGA portion retains all of the features of the ORCA
Series 3 FPGA architecture:
— High-performance, cost-effective, 0.25 μm
five-level metal technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
— Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
— Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL
*
-like AND-OR-INVERT (AOI) in each
programmable logic cell (PLC).
— Up to three ExpressCLK inputs allow extremely
fast clocking of signals on- and off-chip plus
access to internal general clock routing.
— Dual-use microprocessor interface (MPI) can be
used for configuration as well as for a general-pur-
pose interface to the FPGA. Glueless interface to
i960
and PowerPC
processors with user-config-
urable address space provided.
— Programmable clock manager (PCM) adjusts
clock phase and duty cycle for input clock rates
from 5 MHz to 120 MHz. The PCM may be com-
bined with FPGA logic to create complex func-
tions, such as digital phase-locked loops,
frequency counters, and frequency synthesizers
or clock doublers. Two PCMs are provided per
device.
— True
internal 3-state bidirectional buses with sim-
ple control provided by the SLIC.
*
PAL is a trademark of Advanced Micro Devices, Inc.
i960is a registered trademark of Intel Corporation.
PowerPC is a registered trademark of International Business
Machines Corporation.
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| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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