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| 型號(hào)： | OR3C80-5B600 |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, PBGA600 |
| 封裝： | BGA-600 |
| 文件頁(yè)數(shù)： | 140/210頁(yè) |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3C80-5B600 |
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Lucent Technologies Inc.
35
Preliminary Data Sheet, Rev. 1
September 1998
ORCA Series 3 FPGAs
Programmable Input/Output Cells
(continued)
Inputs
As outlined earlier in Table 9, there are six major
options on the PIO inputs that can be selected in the
ORCA Foundry tools. For OR3Cxx devices, the inputs
can be configured as either TTL or CMOS compatible.
OR3Txxx devices have 5 V tolerant I/Os as previously
explained, but can optionally be selected on a pin-by-
pin basis to be PCI bus 3.3 V signaling compliant (PCI
bus 5 V signaling compliance occurs in 5 V tolerant
operation). Inputs may have a pull-up or pull-down
resistor selected on an input for signal stabilization and
power management. Input signals in a PIO can be
passed to PIC routing on any of three paths, two gen-
eral signal paths into PIC routing, and/or a fast route
into the clock routing system.
There is also a programmable delay available on the
input. When enabled, this delay affects the IN1 and IN2
signals of each PIO, but not the clock input. The delay
allows any signal to have a guaranteed zero hold time
when input. This feature is discussed subsequently.
Inputs should have transition times of less than 500 ns
and should not be left floating. If an input can float, a
pull-up or pull-down should be enabled. Floating inputs
increase power consumption, produce oscillations, and
increase system noise. The OR3Cxx inputs have a typ-
ical hysteresis of approximately 280 mV (200 mV for
the OR3Txxx) to reduce sensitivity to input noise. The
PIC contains input circuitry which provides protection
against latch-up and electrostatic discharge.
The other features of the PIO inputs relate to the new
latch/FF structure in the input path. As shown in
latch/register pair. These structures can operate in the
modes listed in Table 9. In latch mode, the input signal
is fed to a latch that is clocked by a system clock sig-
nal. The clock may be inverted or noninverted from its
sense in the PIC routing. There is also a local set/reset
signal to the latch from the PIC routing. The senses of
these signals are also programmable as well as the
capability to enable or disable the global set/reset sig-
nal and select the set/reset priority. The same control
signals may also be used to control the input latch/FF
when it is configured as a FF instead of a latch, with the
addition of another control signal used as a clock
enable.
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| OR3T125-4B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
| OR3T125-4BA352I | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| OR3T125-4BA352 | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| OR3T125-5B432 | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-5BA352 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C805BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-5BA352I | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-5BC432 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-5BC432I | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
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