- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299576 > OR3C80-5B600 FPGA, 484 CLBS, 58000 GATES, PBGA600 PDF資料下載
參數(shù)資料
| 型號： | OR3C80-5B600 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 484 CLBS, 58000 GATES, PBGA600 |
| 封裝： | BGA-600 |
| 文件頁數(shù)： | 112/210頁 |
| 文件大?。?/td> | 2138K |
| 代理商： | OR3C80-5B600 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁當(dāng)前第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁
Preliminary Data Sheet, Rev. 1
ORCA Series 3 FPGAs
September 1998
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
Contents
Page
Features .......................................................................... 1
System-Level Features ................................................... 3
Description ...................................................................... 4
FPGA Overview .......................................................... 4
PLC Logic ................................................................... 4
PIC Logic .................................................................... 5
System Features ......................................................... 5
Routing ....................................................................... 5
Configuration .............................................................. 5
ORCA Foundry Development System ........................ 6
Architecture ..................................................................... 6
Programmable Logic Cells .............................................. 8
Programmable Function Unit ...................................... 8
Look-Up Table Operating Modes .............................. 10
Supplemental Logic and Interconnect
Cell (SLIC) ............................................................ 18
PLC Latches/Flip-Flops ............................................ 22
PLC Routing Resources ........................................... 24
PLC Architectural Description ................................... 31
Programmable Input/Output Cells ................................ 33
5 V Tolerant I/O ......................................................... 34
PCI Compliant I/O ..................................................... 34
Inputs ........................................................................ 35
Outputs ..................................................................... 38
PIC Routing Resources ............................................ 41
PIC Architectural Description .................................... 42
High-Level Routing Resources ..................................... 44
Interquad Routing ..................................................... 44
Programmable Corner Cell Routing .......................... 45
PIC Interquad (MID) Routing .................................... 46
Clock Distribution Network ............................................ 47
PFU Clock Sources .................................................. 47
Clock Distribution in the PLC Array .......................... 48
Clock Sources to the PLC Array ............................... 49
Clocks in the PICs .................................................... 49
ExpressCLK Inputs ................................................... 50
Selecting Clock Input Pins ........................................ 50
Special Function Blocks ................................................ 51
Single Function Blocks ............................................. 51
Boundary Scan ......................................................... 54
Microprocessor Interface (MPI) .................................... 61
PowerPC System ...................................................... 62
i960 System .............................................................. 63
MPI Interface to FPGA .............................................. 64
MPI Setup and Control ............................................. 65
Programmable Clock Manager
(PCM): (Advance Information) ....................................... 69
PCM Registers .......................................................... 70
Delay-Locked Loop (DLL) Mode ............................... 72
Phase-Locked Loop (PLL) Mode .............................. 73
PCM/FPGA Internal Interface ................................... 75
PCM Operation ......................................................... 75
PCM Detailed Programming ..................................... 76
PCM Applications ..................................................... 79
PCM Cautions ........................................................... 80
FPGA States of Operation ............................................ 81
Initialization ............................................................... 81
Configuration ............................................................ 82
Start-Up .................................................................... 83
Reconfiguration ......................................................... 84
Partial Reconfiguration .............................................. 84
Other Configuration Options ..................................... 84
Configuration Data Format ............................................ 85
Using
ORCA Foundry to Generate
Configuration RAM Data ....................................... 85
Configuration Data Frame ......................................... 85
Bit Stream Error Checking ........................................ 87
FPGA Configuration Modes .......................................... 88
Master Parallel Mode ................................................ 88
Master Serial Mode ................................................... 89
Asynchronous Peripheral Mode ................................ 90
Microprocessor Interface (MPI) Mode ....................... 90
Slave Serial Mode ..................................................... 93
Slave Parallel Mode .................................................. 93
Daisy-Chaining .......................................................... 94
Daisy-Chaining with Boundary Scan.......................... 95
Absolute Maximum Ratings .......................................... 95
Recommended Operating Conditions ........................... 95
Electrical Characteristics ............................................... 96
Timing Characteristics ................................................... 98
Description ................................................................ 98
PFU Timing ............................................................. 100
PLC Timing ............................................................. 107
SLIC Timing ............................................................ 107
PIO Timing .............................................................. 108
Special Function Blocks Timing ...............................111
Clock Timing ........................................................... 118
Configuration Timing ............................................... 125
Readback Timing .................................................... 135
Input/Output Buffer Measurement Conditions ............. 136
Output Buffer Characteristics ...................................... 137
OR3Cxx .................................................................. 137
OR3Txxx ................................................................. 138
Estimating Power Dissipation ..................................... 139
OR3Cxx .................................................................. 139
OR3Txxx ................................................................. 140
PCM Power Dissipation ........................................... 141
Pin Information ............................................................ 142
Pin Descriptions ...................................................... 142
Package Compatibility ............................................ 146
Compatibility with OR2C/TxxA Series ..................... 147
Package Thermal Characteristics ................................ 194
ΘJA .......................................................................... 194
ψ JC ......................................................................... 194
ΘJC .......................................................................... 194
ΘJB .......................................................................... 194
FPGA Maximum Junction Temperature ................... 195
Package Coplanarity .................................................... 196
Package Parasitics ...................................................... 196
Package Outline Diagrams .......................................... 197
Terms and Definitions .............................................. 197
208-Pin SQFP.......................................................... 198
208-Pin SQFP2........................................................ 199
240-Pin SQPF.......................................................... 200
240-Pin SQFP2........................................................ 201
256-Pin PBGA.......................................................... 202
352-Pin PBGA.......................................................... 203
432-Pin EBGA.......................................................... 204
600-Pin EBGA.......................................................... 205
Index ............................................................................ 206
Ordering Information ................................................... 209
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3T125-4B432 | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
| OR3T125-4B600 | FPGA, 784 CLBS, 92000 GATES, PBGA600 |
| OR3T125-4BA352I | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| OR3T125-4BA352 | FPGA, 784 CLBS, 92000 GATES, PBGA352 |
| OR3T125-5B432 | FPGA, 784 CLBS, 92000 GATES, PBGA432 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3C80-5BA352 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C805BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3872 LUT 356 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3C80-5BA352I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-5BC432 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3C80-5BC432I | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。