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參數(shù)資料
| 型號(hào)： | OCX160-PPT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | OCX160 Crosspoint Switch |
| 中文描述： | OCX160交叉點(diǎn)開關(guān) |
| 文件頁數(shù)： | 21/44頁 |
| 文件大小： | 710K |
| 代理商： | OCX160-PPT |
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OCX160 Crosspoint Switch
—
Preliminary Data Sheet
I-Cube, Inc.
[Rev. 1.6] 2/20/01
21
2. Pin Description
NOTES:
1.
Dedicated differential input buffers can receive both LVDS and LVPECL voltage levels using
3.3V supply.
2.
V
DD
.PAD is 2.5V for LVDS outputs or 3.3V for LVPECL outputs.
Dedicated differential output buffers can be biased using different supplies for V
DD
.PAD and
external resistors to support both LVDS and LVPECL output voltage levels.
3.
4.
The LVTTL control, JTAG pins, and differential input ports are 3.3V
—
they are not 5V tolerant.
5.
The differential output pins powered from 2.5V are 3.3V tolerant.
Table 12
OCX160 Pin Description
Pin Name
# of Pins
Type
Description
INP[79:0]
80
Input
Non-inverting differential input signals
INN[79:0]
80
Input
Inverting differential input signals
OUTP[79:0]
80
Output
Non-inverting differential input signals
OUTN[79:0]
80
Output
Inverting differential input signals
CLKP
1
Input
Non-inverting differential Global Clock
CLKN
1
Input
Inverting differential Global Clock
OE#
1
Input
Global Output Enable
HW_RST#
1
Input
Hardware Reset
UPDATE#
1
Input
Global Update
RC Pins
RCA[6:0]
7
Input
RapidConfigure Address A
RCB[6:0]
7
Input
RapidConfigure Address B
RCO[4:0]
5
Output
RapidConfigure Readback
RCI[3:0]
4
Input
RapidConfigure Instruction Bits
RC_CLK#
1
Input
RapidConfigure Clock
RC_EN#
1
Input
RapidConfigure Cycle Enable
JTAG Pins
TCK
1
Input
JTAG Test Clock
TMS
1
Input
JTAG Test Mode Select
TDI
1
Input
JTAG Test Data In
TRST#
1
Input
JTAG Test Reset
TDO
1
Output
JTAG Test Data Out
Power and Ground Pins
V
DD
.CORE
V
DD
.PAD
(2, 3)
V
DD
.IN
(1, 4)
12
2.5V Power
Core Voltage
8
2.5V or 3.3V Power
Differential Output Buffer Voltage
8
3.3V Power
LVTTL Control pins Voltage and Differential Input
Buffer Voltage
V
SS
36
Ground
Ground
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