參數(shù)資料
型號: NRF9E5-EVKIT868
廠商: Electronic Theatre Controls, Inc.
英文描述: 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC
中文描述: 433/868/915MHz RF收發(fā)器與8051兼容的嵌入式微控制器和4輸入,10位ADC
文件頁數(shù): 89/104頁
文件大?。?/td> 1436K
代理商: NRF9E5-EVKIT868
PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone +4772898900 - Fax +4772898989
Revision: 1.1
Page 89 of 104
June 2004
18.9.3.2
Mode 2 Receive
Figure 31 illustrates the mode 2 receive timing. Reception begins at the falling edge of a
start bit received on rxd_in, when enabled by the REN bit. For this purpose, rxd_in is
sampled sixteen times per bit for any baud rate. When a falling edge of a start bit is
detected, the divide-by-16 counter used to generate the receive clock is reset to align the
counter rollover to the bit boundaries.
Figure 31 Serial port Mode 2 Receive Timing.
For noise rejection, the serial port establishes the content of each received bit by a
majority decision of three consecutive samples in the middle of each bit time. This is
especially true for the start bit. If the falling edge on rxd_in is not verified by a majority
decision of three consecutive samples (low), then the serial port stops reception and
waits for another falling edge on rxd_in.
At the middle of the stop bit time, the serial port checks for the following conditions:
- RI = 0
- If SM2 = 1, the state of the stop bit is 1
(if SM2 = 0, the state of the stop bit does not matter)
If the above conditions are met, the serial port then writes the received byte to the SBUF
register, loads the 9th received bit into RB8, and sets the RI bit. If the above conditions
are not met, the received data is lost, the SBUF register and RB8 bit are not loaded, and
the RI bit is not set. After the middle of the stop bit time, the serial port waits for another
high-to-low transition on the rxd_in.
18.9.4
Mode 3
Mode 3 provides asynchronous, full-duplex communication, using a total of eleven bits:
- One start bit
- Eight data bits
- One programmable 9th bit
- One stop bit; the data bits are transmitted and received LSB first
The mode 3 transmit and receive operations are identical to mode 2. The mode 3 baud
rate generation is identical to mode 1. That is, mode 3 is a combination of mode 2
protocol and mode 1 baud rate. Figure 32 illustrates the mode 3 transmit timing. Mode 3
operation is identical to that of the standard 8051 when Timers 1 and 2 use CPU_clk/12
(the default).
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