參數(shù)資料
型號(hào)： NRF9E5-EVKIT868
廠商： Electronic Theatre Controls, Inc.
英文描述： 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC
中文描述： 433/868/915MHz RF收發(fā)器與8051兼容的嵌入式微控制器和4輸入，10位ADC
文件頁(yè)數(shù)： 73/104頁(yè)
文件大小： 1436K
代理商： NRF9E5-EVKIT868
PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone +4772898900 - Fax +4772898989
Revision: 1.1
Page 73 of 104
June 2004
18.7
SFR Registers Unique to nRF9E5
The table below lists the SFR registers that are unique to nRF9E5 (not part of standard
8051 register map) The registers P0, P1 and P2 (radio) use the addresses for the ports
P0, P1 and P2 in a standard 8051. Whereas the functionality of these ports is similar to
that of the corresponding ports in standard 8051, it is not identical.
Addr
SFR
80
*
90*
R/W
#bit
Init
hex
FF
FF
Name
Function
R/W
R/W
8
P0
Port 0, pins P07 to P00
8(4)
P1**
Port 1, pins SPI_CSN, SPI_MISO, SPI_MOSI
and SPI_SCK
Direction of each GPIO bit of port 0
Select alternate functions for each pin of port 0
Direction for each GPIO bit of port 1
Select alternate functions for each pin of port 1
General purpose IO for interface to nRF905 radio,
for details see chapter 8.1
PWM control register
PWM duty cycle
High part of 16 bit register for interface to
Watchdog and RTC
Low part of 16 bit register for interface to
Watchdog and RTC
Control of interface to Watchdog and RTC.
Reset status and control
SPI data input/output
00 -> SPI not used 01 -> connect to P1
10 or 11 -> connect to RADIO
Divider from CPU clock to SPI clock
TICK Divider.
Clock control
Test mode register.
This register must always be 0 in normal mode.
Control generation of 4 kHz CKLF
Silicon stepping
94
95
96
97
A0*
R/W
R/W
R/W
R/W
R/W
8
8
FF
00
F4
00
08
P0_DIR
P0_ALT
P1_DIR
P1_ALT
P2
8(4)
8(4)
8
A9
AA
AB
R/W
R/W
R/W
8
8
8
0
0
0
PWMCON
PWMDUTY
REGX_MSB
AC
R/W
8
0
REGX_LSB
AD
B1
B2
B3
R/W
R/W
R/W
R/W
5
2
8
2
0
02
0
0
REGX_CTRL
RSTREAS
SPI_DATA
SPI_CTRL
B4
B5
B6
B7
R/W
R/W
W
R
2
8
3
4
0
SPICLK
TICK_DV
CK_CTRL
TEST_MODE
1D
0
0
BF
FE
R/W
R
6
8
27
00
CKLFCON
HWREV
Table 64 SFR registers unique to nRF9E5.
*
**
This bit addressable register differs in usage from “standard 8051
Only 4 lower bits are meaningful in P1 and corresponding P1_DIR and P1_ALT
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