參數(shù)資料
型號(hào): NRF9E5-EVKIT868
廠商: Electronic Theatre Controls, Inc.
英文描述: 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC
中文描述: 433/868/915MHz RF收發(fā)器與8051兼容的嵌入式微控制器和4輸入,10位ADC
文件頁數(shù): 14/104頁
文件大?。?/td> 1436K
代理商: NRF9E5-EVKIT868
PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone +4772898900 - Fax +4772898989
Revision: 1.1
Page 14 of 104
June 2004
6
DIGITAL I/O PORTS
The nRF9E5 has two IO ports located at the default locations for P0 and P1 in standard
8051, but the ports are fully bi-directional CMOS and the direction of each pin is
controlled by a _DIR and an _ALT bit for each bit as shown in the table below.
Pin
Default function
P1.3
SPI.datain
SPI.clock
SPI.dataout
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Alternate=1
SPI_CTRL != 01
P1.3
P1.2
P1.0
P1.1
EECSN
MISO
SCK
MOSI
P00
P01
P02
P03
P04
P05
P06
P07
T2 (timer2 input)
GTIMER
RXD (UART)
TXD (UART)
INT0_N (interrupt)
INT1_N (interrupt)
T0 (timer0 input)
T1 (timer1 input)
PWM
Table 8 Port functions.
6.1
I/O Port Behavior During RESET
During this period the internal reset is active (regardless of whether or not the clock is
running), all the port pins related to P0 are configured as inputs, whereas the inputs
related to P1 are configured as required for an SPI master. When program execution
starts, all ports are still configured as during reset, and the program will need to set the
_ALT and/or the _DIR register for the pins that need another direction.
6.2
Port 0 (P0)
P0_ALT and P0_DIR control the P0 port function in that order of priority. If the
alternate function for port P0.n is set (by P0_ALT.n = 1) the pin will be input or output
as required by the alternate function (UART, external interrupt, timer inputs or PWM
output), except that the UART RXD direction will still depend on P0_DIR.1.
To use INT0_N or INT1_N as interrupts, the corresponding alternate function must be
activated, P0_ALT.3 / P0_ALT.4. When the P0_ALT.n is not set, bit ‘n’ of the port is a
GPIO function with the direction controlled by P0_DIR.n.
Data in P0_ALT.n,P0_DIR.n
11
GTIMER
Out
RXD
In
TXD
Out
INT0_N
In
INT1_N
In
T0
In
T1
In
PWM
Out
Pin
10
00
01
P00
P01
P02
P03
P04
P05
P06
P07
GTIMER
RXD
TXD
INT0_N
INT1_N
T0
T1
PWM
Out
Out
Out
In
In
In
In
Out
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Out
Out
Out
Out
Out
Out
Out
Out
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
In
In
In
In
In
In
In
In
Table 9 Port 0 (P0) functions.
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