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參數(shù)資料
| 型號： | NCV7380DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSCEIVER LINEAR 8-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 21/Jun/2007 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | LIN |
| 電源電壓： | 7 V ~ 18 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 帶卷 (TR) |
NCV7380
http://onsemi.com
10
Recommendations for System Design
The goal of the LIN physical layer standard is to have a
universal definition of the LIN system for plug and play
solutions in LIN networks up to 20 kBd bus speeds.
In case of small and medium LIN networks, it’s
recommended to adjust the total network capacitance to at
least 4.0 nF for good EMC and EMI behavior. This can be
done by setting only the master node capacitance. The
slave node capacitance should have a unit load of typically
220 pF for good EMC/EMI behavior.
In large networks with long bus lines and the maximum
number of nodes, some system parameters can exceed the
defined limits and the LIN system designer must intervene.
The whole capacitance of a slave node is not only the unit
load capacitor itself. Additionally, there is the capacitance
of wires and connectors, and the internal capacitance of the
LIN transmitter. This internal capacitance is strongly
dependent on the technology of the IC manufacturer and
should be in the range of 30 pF to 150 pF. If the bus lines
have a total length of nearly 40m, the total bus capacitance
can exceed the LIN system limit of 10 nF.
A second parameter of concern is the integrated slave
termination resistor tolerance. If most of the slave nodes
have a slave termination resistance at the allowed
maximum of 60 k
W, the total network resistance is more
than 700
W. Even if the total network capacitance is below
or equal to the maximum specified value of 10 nF, the
network time constant is higher than 7.0
ms.
This problem can be solved only by adjusting the master
termination resistor to the required maximum network time
constant of 5.0
ms (max).
NOTE: The NCV7380 meets the requirements for
implementation in RCbased slave nodes. The LIN
Protocol Specification requires the deviation of the slave
node clock to the master node clock after synchronization
must not differ by more than
"2%.
Setting the network time constant is necessary in large
networks (primarily resistance) and also in small networks
(primarily capacitance).
MIN/MAX SLOPE TIME CALCULATION
(In accordance to the LIN System Parameter Table)
Figure 7. Slope Time and Slew Rate Calculation
(In accordance to LIN physical layer specification 1.3)
60%
100%
0%
tsrec
tsdom
VBUS
40%
Vdom
60%
40%
The slew rate of the bus voltage is measured between
40% and 60% of the output voltage swing (linear region).
The output voltage swing is the difference between
dominant and recessive bus voltage.
dV dt + 0.2 * Vswing (t40%t60%)
The slope time is the extension of the slew rate tangent
until the upper and lower voltage swing limits:
tslope + 5* (t40%t60%)
The slope time of the recessive to dominant edge is directly
determined by the slew rate control of the transmitter:
tslope + Vswing dV dt
The dominant to recessive edge is influenced from the
network time constant and the slew rate control, because it’s
a passive edge. In case of low battery voltages and high bus
loads the rising edge is only determined by the network. If the
rising edge slew rate exceeds the value of the dominant one,
the slew rate control determines the rising edge.
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