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參數(shù)資料
| 型號(hào)： | NCV7380DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 13/14頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSCEIVER LINEAR 8-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 21/Jun/2007 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | LIN |
| 電源電壓： | 7 V ~ 18 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 帶卷 (TR) |
NCV7380
http://onsemi.com
8
Functional Description
Initialization
After power on, the chip automatically enters the
recessive state (TxD = Open). Both VCC and VS must
be present.
Operating Modes
All operation modes will be handled from the
NCV7380 automatically.
Normal Mode
After power on, the IC switches automatically to normal
mode. Bus communication is possible. If there is no
communication on the bus line the power consumption of
the
IC
is
very
low
and
does
not
require
microprocessor control.
Thermal Shutdown Mode
If the junction temperature TJ is higher than 155°C, the
NCV7380 could be switched into the thermal shutdown
mode (bus driver will be switched off, receiver is on).
If TJ falls below the thermal shutdown temperature
(typical 140
°C) the NCV7380 will be switched to the
normal mode.
LIN BUS Transceiver
The transceiver consists of a busdriver (1.2 V @
40 mA) with slew rate control and current limit, and a
receiver
with a high voltage comparator with
filter circuitry.
BUS Input/Output
The recessive BUS level is generated from the integrated
30 k pullup resistor in series with a diode. The diode
prevents reverse current on VBUS when VBUS > VS.
No additional termination resistor is necessary to use the
NCV7380 on LIN slave nodes. If this IC is used for LIN
master nodes, it is necessary to terminate the bus with an
external 1.0 k
W resistor in series with a diode to VBAT
(Figure 9).
TxD Input
During transmission the signal on TxD will be
transferred to the BUS driver for generating a BUS signal.
To minimize the electromagnetic emission of the bus line,
the BUS driver has integrated slew rate control and
wave shaping.
Transmitting will be interrupted if thermal shutdown
is active.
The CMOS compatible input TxD directly controls the
BUS level:
TxD = low
→ BUS = low (dominant level)
TxD = high
→ BUS = high (recessive level)
The TxD pin has an internal pullup resistor connected to
VCC. This secures that an open TxD pin generates a
recessive BUS level.
RxD Output
The signal on the BUS pin will be transferred
continuously to the RxD pin. Short spikes on the bus signal
are filtered with internal circuitry (Figure 3 and Figure 6).
Figure 6. Receive Impulse Diagram
60%
t < trec_deb
VS
RxD
40%
t < trec_deb
BUS
50%
VBUS_CNT_max
VBUS_CNT_min
VhHYS
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