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參數(shù)資料
| 型號： | NCV7361ADR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | Buffer和線驅(qū)動 |
| 英文描述： | Voltage Regulator with Integrated LIN Transceiver; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | LINE TRANSCEIVER, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 5/27頁 |
| 文件大?。?/td> | 272K |
| 代理商： | NCV7361ADR2G |
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NCV7361A
http://onsemi.com
13
VSUP Undervoltage in Sleep Mode
No exit from the sleep mode will take place if the VSUP
voltage drops down to VSUVR_ON (typical 3.0 V). The
undervoltage reset becomes active (PORstate). As a result
of this operating, the sleep mode is left to the normal mode.
If VSUP rises again above VSUVR_OFF (typical 3.5 V), the
IC initializes the voltage regulator and continues to work
with the normal mode.
The undervoltage reset unit secures stable operating in
the undervoltage range of VSUP down to GND level. The
dynamic PowerOnReset secures a defined internal state
independent from the duration of the VSUP drop, which
secures a stable restart.
Overtemperature Shutdown
If the junction temperature is 155
°C < TJ < 170°C the
overtemperature recognition will be activated and the
regulator voltage will be switched off. The VOUT voltage
drops down, the reset state is entered and the
bustransceiver is switched off (recessive state).
After TJ falls below 140°C the NCV7361A will be
initialized again (Figure 17) independently from the
voltage levels on EN and BUS. Within the thermal
shutdown mode the transceiver can not be switched to the
normal mode neither with local nor with remote wakeup.
The operation of the NCV7361A is possible between
TAmax (125°C) and the switchoff temperature, but small
parameter differences can appear.
After overtemperature switchoff the IC behaves as
described in Figure 17.
LIN BUS Transceiver
The NCV7361A is a bidirectional bus interface device
for data transfer between the LIN bus and the LIN protocol
controller.
The transceiver consists of a pnpdriver (1.2 V @
40 mA) with slew rate control, wave shaping and current
limit, and a high voltage receiver/comparator followed by
a filter circuit.
Transmit Mode
During transmission the data at the TxD pin will be
transferred to the BUS driver for generating a BUS signal.
To minimize the electromagnetic emission of the bus line,
the BUS driver has integrated slew rate control and wave
shaping circuitry.
Transmitting will be interrupted in the following cases:
Sleep Mode
Thermal Shutdown Active
Master Reset (VOUT < 3.15 V)
The recessive BUS level is generated from the integrated
30 k pullup resistor in series with a diode This diode
prevents reverse current on VBUS when VBUS > VSUP.
No additional termination resistor is necessary to use the
NCV7361A in LIN slave nodes. If this IC is used for LIN
master nodes, it is necessary to terminate the bus pin with
an external 1.0 k
W resistor in series with a diode to VBAT.
Receive Mode
The data signal from the BUS pin will be transferred
continuously to the pin RxD. Short spikes on the bus are
suppressed by the internal filter circuit (
t = 2.8 ms).
Figure 17. RESET Behavior
trr
tRes
VSUP
RESET
VRES
VOUT
tRes
T>TJ
T<TJ
t<trr
tRes
t<trr
tRes
Initialization
Thermal
shutdown
Spike VSUP
Low voltage
VSUP
Current limitation
active
Spike VCC
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