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參數(shù)資料
| 型號(hào)： | NCV7361ADR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | Buffer和線驅(qū)動(dòng) |
| 英文描述： | Voltage Regulator with Integrated LIN Transceiver; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | LINE TRANSCEIVER, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁(yè)數(shù)： | 11/27頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | NCV7361ADR2G |
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NCV7361A
http://onsemi.com
19
MIN/MAX SLOPE TIME CALCULATION
Figure 27. Slope Time Calculation
95%
100%
0%
tsrec
tsdom
VBUS
40%
Vdom
60%
5%
BUS
The slew rate of the bus voltage is measured between
40% and 60% of the output voltage swing (linear region).
The output voltage swing is the difference between
dominant and recessive bus voltage.
dV dt + 0.2 * Vswing (t40%t60%)
The slope time is the extension of the slew rate tangent
until the upper and lower voltage swing limits:
tslope + 5* (t40%t60%)
The slope time of the recessive to dominant edge is directly
determined by the slew rate control of the transmitter:
tslope + Vswing dV dt
The dominant to recessive edge is influenced from the
network time constant and the slew rate control, because
it’s a passive edge. In case of low battery voltages and high
bus loads the rising edge is only determined by the network.
If the rising edge slew rate exceeds the value of the
dominant one, the slew rate control determines the rising
edge.
Power Dissipation and Operating Range
The max power dissipation depends on the thermal
resistance of the package and the PCB, the temperature
difference between Junction and Ambient as well as the
airflow.
The power dissipation can be calculated with:
PD + (VSUP * VOUT)* IVOUT ) PD_TX
The power dissipation of the transmitter PD_TX depends
on the transceiver configuration and its parameters as well
as on the bus voltage VBUS = VBAT VD, the resulting
termination resistance RL, the capacitive bus load CL and
the bit rate. Figure 28 shows the dependence of power
dissipation of the transmitter as function of VSUP. The
conditions for calculation the power dissipation was:
RL = 500 W, CL = 10 nF, Bitrate = 20 kbit and duty cycle
on TxD of 50%.
Figure 28. Power Dissipation LIN Transceiver
@ 20 kbit
5
50
17
40
18
15
14
VSUP (V)
P
D
(mW)
30
10
0
616
19
7
20
45
35
25
5
15
13
12
11
10
89
The permitted package power dissipation can be
calculated:
PDmax +
TJ * TA
RqJA
If we consider that PD_TX_max = f(VSUP), it can be
calculated the max output current IVOUT on VOUT:
IVOUTmax +
TJTA
RqJA * PD_TX_max @ VSUP
VSUP * VOUT
TJTA is the temperature difference between junction
and ambient, and Rth is the thermal resistance of the
package. The thermal energy is transferred via the package
and the pins to the ambient. This transfer can be improved
with additional ground areas on the PCB as well as ground
areas under the IC.
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參數(shù)描述 |
|---|---|
| NCV7380 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:LIN Transceiver |
| NCV7380/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LIN Transceiver |
| NCV7380_07 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:LIN Transceiver |
| NCV7380D | 功能描述:IC TRANSCEIVER LINEAR 8-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| NCV7380DG | 功能描述:IC TRANSCEIVER LINEAR 8-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
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