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參數(shù)資料
| 型號： | NCP1651DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 29/32頁 |
| 文件大?。?/td> | 779K |
| 描述： | IC PFC CONTROLLER CCM/DCM 16SOIC |
| 標準包裝： | 1 |
| 模式： | 連續(xù)導電（CCM），間歇導電（DCM） |
| 頻率 - 開關： | 25kHz ~ 250kHz |
| 電流 - 啟動： | 8.5mA |
| 電源電壓： | 10 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 標準包裝 |
| 其它名稱： | NCP1651DR2GOSDKR |
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NCP1651
http://onsemi.com
29
Loop Compensation
Figure 43. Voltage Regulation Loop
--
+
REFERENCE
MULTIPLIER
PWM
OUT
1
LOGIC
V
ref2
4 V
I
S+
Q1
5
C.S. Amp
--
+
25 k
AC
ERROR
AMP
R
S
R
7
7
I
avg
V
ref
DIVIDER
ERROR AMP
REFERENCE SIGNAL
MODULATOR AND OUTPUT STAGE
V2
V
o
=
R
dc2
R
dc1
+ R
dc2
f
z
=
1
2 ?C
fb
R
fb
A
v
=
1
2 ?f C
fb
R
dc1
擵
ref
擵
fb
= 2.66 V
ac
V
ac
=
V
line
R
ac2
R
ac1
+ R
ac2
擵
out
擨
in
=
r
N
p
N
s
u
?R
L
r
T t
on
t
on
u
R
dc1
R
dc2
f
p
=
1
2 ?R
L
R
ac1
R
L
C
V
o
V
ac
V?/DIV>
V
line
I
in
N
p
: N
s
R
ac2
C
10
10
Ref Fltr
--
+
R
opto
R
fb
C
fb
ERROR
AMP
V
ea
0.022 mF
C
8
6.5 V
3.8 k
OPTO TRANSFER
擵
fb
擵
ea
=
3.8 k CTR
R
opto
A
v
= R
fb
R
dc1
for f > f
z
:
for f < f
z
:
擨
in
擵
ref
=
R
7
R
S
75,000
V
fb
FB/SD
8
Loop Model
Themodelforthevoltageloophasbeenbrokendowninto
six sections. The voltage divider, error amplifier, and opto
Transfer are external to the chip, and the reference signal,
modulator and output stage are internal.
The modulator and output stage circuitry is greatly
simplifiedbasedontheassumptionthatthatpolesandzeros
in the current feedback loop are considerably greater than
the bandwidth of the overall loop. This should be a good
assumption, because a bandwidth in the kilohertz is
necessaryforagoodcurrentwaveform,andthevoltageerror
amplifier needs to have a bandwidth of less than the lowest
line frequency that will be used.
There are two poles in this circuit. The output filter has a
pole that varies with the load. The pole on the voltage error
amplifier will be determined by this analysis.
Voltage Divider
The voltage divider is located on the secondary side
circuitry. It is a simple resistive divider that reduces the
outputvoltagetothelevelrequiredbytheinternalreference
on the voltage error amplifier. If the amplifier circuit of
Figure 42 is used, there are four resistors instead of 2. To
determine the gain of this circuit, R
dc1
is the equivalent of
the upper two resistors, 9.31 k and 453 Ohms respectively,
andR
dc2
istheequivalentofthelowertworesistors,422and
5.23 k respectively.
Voltage Error Amplifier
The voltage error amplifier is constrained by the two
equations. When this amplifier is compensated with a
pole- -zero pair, there will be a unity gain pole which will be
cancelled by the zero at frequency f
z
. The corresponding
bode plot would be:
Figure 44. Pole- -zero Bode Plot
f, FREQUENCY
20
0
- -20
Unity Gain
A
V
f
z
The gain at frequencies greater than f
z
is determined by
R
fb
. Once R
fb
is determined, the value of C
fb
can be easily
calculated using the formula for f
z
.
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