參數(shù)資料
型號(hào)： NCP1651DR2G
廠(chǎng)商： ON Semiconductor
文件頁(yè)數(shù)： 22/32頁(yè)
文件大?。?/td> 779K
描述： IC PFC CONTROLLER CCM/DCM 16SOIC
標(biāo)準(zhǔn)包裝： 1
模式： 連續(xù)導(dǎo)電（CCM），間歇導(dǎo)電（DCM）
頻率 - 開(kāi)關(guān)： 25kHz ~ 250kHz
電流 - 啟動(dòng)： 8.5mA
電源電壓： 10 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： NCP1651DR2GOSDKR
NCP1651
http://onsemi.com
22
Thereisahysteresisof30癈onthiscircuit,whichwillallow
the chip to cool down to 130癈 before resuming operation.
Whileintheovertemperatureshutdownmode,thestartup
circuit will be operational and the V
CC
will cycle between
10.8 and 9.8 volts.
Insufficient V
CC
If the level of the V
CC
voltage is not
sufficienttomaintainoperation,thedriveofthechipwillbe
inhibited and the divide- -by- -eight timer will be invoked.
This will normally occur when the output is overloaded.
Underthiscondition,thedivide- -by- -eightcounterwillcount
for 8 V
CC
cycles. At the end of the eighth cycle the driver
will be enabled and the circuit will attempt to start. If the
failure has been corrected, the output will come up and the
circuit will resume normal operation. If not, another cycle
will begin. The waveforms for overload timeout are shown
in Figure 3.
Shutdown
The NCP1651 has a shutdown circuit that
can be used to inhibit the operation of the chip by reducing
the FB/SD pin voltage to less than 0.6 volts. When a
shutdown signal is issued, the output of the shutdown
comparatorgoeslow.Thisimmediatelyceasestheoperation
of the unit by ORing that signal to the output of the PWM
logic, and holding the driver in its low state.
The inverted output of the shutdown comparator isfed in
to the reset pin of the divide- -by- -eight counter. The counter
reset pin sets its count to seven. As long as the reset pin is
low, the counter will remain at seven. When the shutdown
signalisremoved,theresetpinwillgohigh,andthecounter
will continue to count to eight. The counter is triggered on
the negative edge of the startup enable signal. This means
that a shutdown signal that is removed on the upward V
CC
slopewillbeinthe7countfor theremainingriseandfallof
that V
CC
cycle and will change to 8 on the next cycle.
Thissystemassuresthat the unit will not be enabled until
the V
CC
voltage has a full discharge cycle available, and it
also insures that the unit will commence operation in less
than two V
CC
cycles. A timing diagram of this mode of
operation  is  shown  in  Figure  3.  The  count  for  the
divide- -byeight counter is shown as 7, 7, 7, 8 which
illustrates the operation of the reset function.
If theshutdownsignalisterminatedbeforethe V
CC
voltage
reaches the lower UVLO limit (i.e. 9.8 volts), the unit will
resumeoperationonthefollowingV
CC
downslope,andifthe
shutdown signal is terminated on the V
CC
upward slope, the
unit will resume operation on the second V
CC
down slope.
AC Reference Buffer
The AC reference buffer converts the voltage generated
by the AC error amplifier to be converted into a current to
be summed with the ramp compensation signal and the
instantaneous current signal.
Figure 37. AC Reference Buffer Schematic
CURRENT
MIRROR
--
+
i
1
i
1
--
+
16 k
6.7 k
2.9 V
Unity Gain Amplifier
AC
ERROR
AMP
AC
Comp
3
PWM,
Ramp
Comp
Current
Sense
Amp
The buffers transfer function is:
i
out
= (2.9 V  V
ac(ea)
)6.7 k
The buffer amplifier, converts the input voltage to a
current by creating a current equal to the voltage difference
between the AC error amplifier output and the 2.9 volt
reference dropped across the 6.7 k?resistor. The bipolar
transistor level shifts the voltage and maintains the proper
current into the current mirror. The current mirror has a
1:1 ratio and delivers its output current to the PWM input.
This current is summed with the currents of the ramp
compensationsignalandtheinstantaneouscurrentsignalto
determine the turn- -off point in the switching cycle.
Startup Circuit
Thestartupcircuitservesseveralfunctions.Inadditionto
providing the initial charge on the V
CC
capacitor, it serves
asatimer for thestartup,overcurrent,andshutdownmodes
ofoperation.Duetothenatureofthiscircuit,thischipmust
be biased using the startup circuit and an auxiliary winding
on the power transformer. Attempting to operate this chip
off of a fixed voltage supply will cause the chipto latchup
in some modes of operation.
A high voltage FET is biased as a current source to provide
current for startup power. On the application of input voltage,
thehighvoltagestartupcircuitisenabledandcurrentisdrawn
from the rectified AC line to charge the V
CC
cap.
WhenthevoltageontheV
CC
capreachestheturnonpoint
for the UVLOcircuit (10.8voltstypical),the startupcircuit
is disabled, and the PWM circuit is enabled. With the
NCP1651 enabled, the bias current increases from its
standby level to the operational level. The divide- -by- -eight
counterispresettothecountof7,sothatonstartupthechip
will not be operational on the first cycle. The second V
CC
cyclewillbenumber 8, andthe chipwill beallowed tostart
at thistime. In the shutdown mode, the V
CC
cycle is held in
the 7 count state until the shutdown signal is removed. This
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