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參數(shù)資料
| 型號： | NCP1651DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 779K |
| 描述： | IC PFC CONTROLLER CCM/DCM 16SOIC |
| 標準包裝： | 1 |
| 模式： | 連續(xù)導(dǎo)電（CCM），間歇導(dǎo)電（DCM） |
| 頻率 - 開關(guān)： | 25kHz ~ 250kHz |
| 電流 - 啟動： | 8.5mA |
| 電源電壓： | 10 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 標準包裝 |
| 其它名稱： | NCP1651DR2GOSDKR |
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NCP1651
http://onsemi.com
21
Theinputtothecurrentsenseamplifierisacommonbase
configuration. The voltage developed across the current
shunt is sensed at the Is+ input. The amplifier input is
designed for positive going voltages only; the power stage
should resemble the configuration of the applicationcircuit
in Figure 38.
Caution should be exercised when designing a filter
between the shunt resistor and this input, due to the low
impedance of this amplifier. Any series resistance due to a
filter, will create an offset of:
V
OS
= 50 mA ?R
external
whichwilladdapositiveoffsettothecurrentsignal.Theeffect
ofthisisthattheACerror amplifierwilltrytocompensatefor
the average output current which appears never to go to zero,
and cause additional zero crossing distortion.
The voltage across the current shunt resistor is converted
intoacurrent(i
1
),whichdrivesacurrentmirror.Theoutput
of the i
1
current mirror is a high frequency signal that is a
replica of the instantaneous current in the switch. The
conversion of the current sense signal to current i
1
is:
i
1
= Vi
s+
3 k
The PWM output sends that information directly to the
PWMinputwhereitisaddedtotheACerrorampsignaland
the ramp compensation signal.
The Leading Edge Blanking circuit (LEB) interrupts the
currentsignaltothePWMcomparatorforthefirst200nsof
the switching pulse. This blanks out any spike that might
occur at turn on, which could cause false triggering of the
PWM comparator.
Theotheroutputofthei
1
mirrorprovidesavoltagesignal
to a buffer amplifier. This signal is the result of i
1
dropped
acrossaninternal30 k﹔esistor,andfilteredbyacapacitor
at pin 6. This signal, when properly filtered, will be the 2x
line frequency fullwave rectified sinewave. The filter pole
onpin6shouldbefarenoughbelowtheswitchingfrequency
to remove most of the high frequency component, but high
enough above the line frequency so as not to cause
significant distortion to the input fullwave rectified
sinewave waveform.
For a 100 kHz switching frequency and a 60 Hz line
frequency, a 10 kHz pole will normally work well. The
capacitoratpin6canbecalculatedknowingthedesiredpole
frequency by the equation:
C
6
=
1
2 ?f30k
Where:
C
6
= Pin 6 capacitance (nF)
f = pole frequency (kHz)
or, for a 10 kHz pole, C
6
would be 0.5 nF.
The gain of the low frequency current buffer is set by the
valueoftheresistoratpin7.ThevalueofR7determinesthe
scale factor between the peak current and the average
current. The average current will be that of the primary
waveformonly,sincethesecondarycurrentwillnotconduct
across the shunt resistor.
PWM Logic
The PWM and logic circuits are comprised of a PWM
comparator, an RS flip- -flop (latch) and an OR gate. The
latch is Set dominant which means that if both R and S are
high the S signal will dominate and Q will be high, which
will hold the power switch off.
The NCP1651 uses a voltage mode Pulse Width
Modulation scheme based on a fixed frequency oscillator.
The oscillator outputs a ramp waveform as well as a pulse
which is coincident with the falling edge of the ramp. The
pulse is fed into the PWM latch and OR gate that follows.
Duringthepulse,thelatchisreset,andtheoutputdriveisin
its low state.
Onthefallingedgeofthepulse,theoutputdrivegoeshigh
andthepowerswitchbeginsconduction.Theinstantaneous
inductor current is summed with the AC error amplifier
voltage and the ramp compensation signal to create a
complexwaveformthatiscomparedtothe4.0voltreference
signalontheinvertinginputtothePWMcomparator.When
thesignalatthenon- -invertinginputtothePWMcomparator
exceeds 4.0 volts, the output of the PWM comparator
changestoa highstate whichdrivesoneof theSet inputsto
the latch and turns the power switch off until the next
oscillator cycle.
The OR gate that follows the PWM is used to inhibit the
drivesignaltothepowerswitch.Inadditiontotheoscillator
pulse,thisgatereceivesasignalfromtheshutdownORgate,
which can inhibit operation due to an overtemperature
condition, shutdown signal, or insufficient V
CC
.
Driver
The output driver can be used to directly drive a FET, for
low and medium power applications, or a larger driver for
high power applications.
It is a complementary MOS, totem pole design, and is
capableofsourcingandsinkingover1.5amps,withtypical
riseandfalltimesof50nswitha1.0nFload.Thetotempole
output has been optimized to minimize cross conduction
current during high speed operation.
Additional internal circuitry has been added to keep the
Driver in its low state whenever the Undervoltage Lockout
is active. This characteristic eliminates the need for an
external gate pulldown resistor.
Shutdown Modes and Logic
Overtemperature
Atemperaturesensorandreferenceis
provided to monitor the junction temperature of the chip.
The chip will operate to a nominal temperature of 160癈 at
whichtimetheoutputofthetemperaturesensorwillchange
to a low state. This will set the output of the shutdown
NAND gate high, which in turn will set the output of the
PWM OR gate high, and force the driver into a low state.
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