參數(shù)資料
型號(hào)： NCN6004AFTBR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 37/40頁(yè)
文件大小： 0K
描述： IC INTERFACE SAM/SIM DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： PC，PDA
接口： 微控制器
電源電壓： 1.8 V ~ 5.5 V
封裝/外殼： 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
安裝類型： 表面貼裝
其它名稱： NCN6004AFTBR2GOSDKR
NCN6004A
http://onsemi.com
6
PIN DESCRIPTION (continued)
Pin
Description
Type
Symbol
18
RESET_B
INPUT
The signal present on this pin is translated to the RST pin of the external smart card #B.
The CS signal must be Low to valid the RESET function, regardless of the selected card.
Assuming the
mP provides two independent lines to control the RESET pins, and
MUX_MODE = Low, the NCN6004A can control two cards simultaneously.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is connected to
VCC, (regardless of the logic state of EN_RPU), and the access to card B takes place by
RESET_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to VCC (EN_RPU = H) or
disconnected when EN_RPU = Low.
19
I/O_B
INPUT/OUTPUT
This pin carries the data transmission between an external microcontroller and the
external smart card #B.
A builtin bidirectional level translator adapts the signal flowing between the card and
the MCU. The level translator is enabled when CS = Low. The signal present on this pin
is latched when CS = High. Since a dedicated line is used to communicate the data
between the
mP and the smart card, (assuming MUX_MODE = Low) the user can
activate the two channels simultaneously, assuming the
mP provides a pair of I/O lines.
When MUX_MODE = High, this pin is internally disable, the pull up resistor is connected
to VCC, (regardless of the logic state of EN_RPU), and the access to card B takes place
by I/O_A associated with CARD_SEL selection bit.
20
CRD_DET_A
INPUT
This pin senses the signal coming from the external smart card connector to detect the
presence of card #A. The polarity of the signal is programmable as Normally Open or
Normally Close switch. The logic signal will be activated when the level is either Low or
High, with respect to the polarity defined previously. By default, the input is Normally
Open. A builtin circuit prevents uncontrolled short pulses to generate an INT signal.
The digital filter eliminates pulse width below 50
ms (see spec).
21
CRD_C8_A
OUTPUT
This pin controls the card #A C8 contact, according to the ISO7816 specifications. A
builtin level shifter is used to adapt the card and the
mC, regardless of the power supply
voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL =L, or CS = H or
PGM = L, and resume to a transparent mode when card #A is selected and operates in
the transfer mode.The pin is hardwired to zero, the bias being provided by the VCC
supply, when either the VCC voltage drops below 2.7 V, or during the CRD_VCC_A
startup time.
22
CRD_C4_A
OUTPUT
This pin controls the card #A C4 contact, according to the ISO7816 specifications. A
builtin level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL = L, or CS = H, or
PGM = L, and resume to a transparent mode when card #A is selected and operates in
the transfer mode.
The pin is hardwired to zero, the bias being provided by the VCC supply, when either the
VCC voltage drops below 2.7 V, or during the CRD_VCC_A startup time.
23
CRD_RST_A
OUTPUT
This pin is connected to the external smart card #A to support the RESET signal. A
builtin level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL = Low, or when CS or
PGM returns to a High, and resume to a transparent mode when card #A is selected. The
pin is hardwired to zero, the bias being provided by the VCC supply, when either the VCC
voltage drops below 2.7 V, or during the CRD_VCC_A startup time.
24
CRD_IO_A
INPUT/OUTPUT
This pin carries the data serial connection between the external smart card #A and the
microcontroller. A builtin bidirectional level shifter is used to adapt the card and the
MCU, regardless of the power supply voltage of each signals.
This pin is biased by a pull up resistor connected to CRD_VCC_A. When CS = High, the
CRD_IO_A holds the previous I/O logic state and resume to a normal operation when this
pin is reactivated.
The pin is hardwired to zero, the bias being provided by the VCC supply, when either the
VCC voltage drops below 2.7 V, or during the CRD_VCC_A startup time.
25
PWR_GND
POWER
This pin carries the power current flow coming from the built in DC/DC converters. It is
associated with the external card # A. It must be connected to the system Ground and care
must be observed at PCB layout level to avoid the risk of spike voltages on the logic lines.
26
L2_A
POWER
Connects one side of the external DC/DC converter inductor #A (Note 1).
27
L1_A
POWER
Connects one side of the external DC/DC converter inductor #A (Note 1).
1. The external inductors shall preferably have the same values. Depending upon the power absorbed by the load, the inductor can range
from 10
mH to 47 mH. To achieve the highest yield, the inductor shall have an ESR < 1.0 W.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NCN6010 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SIM Card Supply and Level Shifter
NCN6010/D 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SIM Card Supply and Level Shifter
NCN6010_06 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SIM Card Supply and Level Shifter
NCN6010D 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:SIM Card Supply and Level Shifter
NCN6010DTB 功能描述:轉(zhuǎn)換 - 電壓電平 2.7V Sim Card RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8
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