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參數(shù)資料
| 型號： | NB3N3001 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3 V 106.25 MHz/ 212.5 MHz PureEdge Clock Generator with LVPECL Differential Output(帶LVPECL差分輸出的3.3V 106.25MHz/212.5MHz PureEdge 時鐘生成器) |
| 中文描述： | 3.3伏106.25兆赫/ 212.5兆赫的PureEdge時鐘發(fā)生器可與LVPECL差分輸出（帶的LVPECL差分輸出的3.3 106.25MHz/212.5MHz的PureEdge時鐘生成器） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 114K |
| 代理商： | NB3N3001 |
NB3N3001
http://onsemi.com
7
PC Board Layout Example
Figure 11 shows a representative board layout for the
NB3N3001. There exists many different potential board
layouts and the one pictured is but one. The crystal X1
footprint shown in this example allows installation of either
surface mount HC49S or throughhole HC49 package. The
footprints of other components in this example are listed in
Table 11. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located
as close as possible to the power pins. The layout assumes
that the board has clean analog power ground plane. The
important aspect of the layout in Figure 11 is the low
impedance connections between V
CC
and GND for the
bypass capacitors. Combining good quality general purpose
chip capacitors with good PCB layout techniques will
produce effective capacitor resonances at frequencies
adequate to supply the instantaneous switching current for
the NB3N3001 outputs. It is imperative that low inductance
chip capacitors are used. It is equally important that the
board layout not introduce any of the inductance saved by
using the leadless capacitors. Thin interconnect traces
between the capacitor and the power plane should be
avoided and multiple large vias should be used to tie the
capacitors to the buried power planes. Fat interconnect and
large vias will help to minimize layout induced inductance
and thus maximize the series resonant point of the bypass
capacitors.
The voltage amplitude across the crystal is relatively
small. It is imperative that no actively switching signals
cross under the crystal as crosstalk energy coupled to these
lines could significantly impact the jitter of the device.
Table 11. Footprint Table
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
Figure 11. PC Board Layout
C2
C1
Figure 12. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
Q
D
Q
D
Z
o
= 50
Z
o
= 50
50
50
V
TT
V
TT
= V
CC
2.0 V
ORDERING INFORMATION
Device
Package
Shipping
NB3N3001DTG
TSSOP8 4.4 mm
(PbFree)
100 Units / Rail
NB3N3001DTR2G
TSSOP8 4.4 mm
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PDF描述 |
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| NB4N840M | 3.3V 2.7Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination(帶CML輸出和內(nèi)部終端的3.3V，2.7Gb/s雙差分時鐘/數(shù)據(jù)2x2交點開關(guān)) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB3N3001DTG | 功能描述:時鐘合成器/抖動清除器 XTAL LVPECL FIBR CLK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| NB3N3001DTR2G | 功能描述:時鐘合成器/抖動清除器 XTAL LVPECL FIBR CLK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| NB3N3002 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V, Crystal-to-HCSL Clock Generator |
| NB3N3002DTG | 功能描述:鎖相環(huán) - PLL CLK GEN LVPECL DIFF OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NB3N3002DTR2G | 功能描述:鎖相環(huán) - PLL CLK GEN LVPECL DIFF OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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