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參數(shù)資料
| 型號： | NB3N3001 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3 V 106.25 MHz/ 212.5 MHz PureEdge Clock Generator with LVPECL Differential Output(帶LVPECL差分輸出的3.3V 106.25MHz/212.5MHz PureEdge 時鐘生成器) |
| 中文描述： | 3.3伏106.25兆赫/ 212.5兆赫的PureEdge時鐘發(fā)生器可與LVPECL差分輸出（帶的LVPECL差分輸出的3.3 106.25MHz/212.5MHz的PureEdge時鐘生成器） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 114K |
| 代理商： | NB3N3001 |
NB3N3001
http://onsemi.com
6
APPLICATION INFORMATION
Power Supply Filtering
The NB3N3001 is a mixed analog/digital product, and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NB3N3001 also
generates subnanosecond output edge rates, and therefore,
a good power supply bypassing scheme is a must.
The NB3N3001 provides separate power supplies for the
digital circuitry (V
CC
) and the internal PLL (V
CCA
). The
simplest form of noise isolation is a power supply filter on
the V
CCA
pin.
Figure 8 illustrates a typical power supply filter scheme.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL.
The purpose of this design technique is to try and isolate
the high switching noise of the digital outputs from the
relatively sensitive internal analog phaselocked loop. The
power supply filter and bypass schemes discussed in this
section should be adequate to eliminate power supply
noiserelated problems in most designs.
Crystal Oscillator Input Interface
The NB3N3001 features an integrated crystal oscillator to
minimize system implementation costs. The oscillator
circuit is a parallel resonant circuit and thus, for optimum
performance, a parallel resonant crystal should be used.
As the oscillator is somewhat sensitive to loading on its
inputs, the user is advised to mount the crystal as close to the
NB3N3001 as possible to avoid any board level parasitics.
Surface mount crystals are recommended, but not required.
Figure 9 illustrates a parallel resonant crystal with its
associated load capacitors. The capacitor values shown were
determined using a 26.5625 MHz, 18 pF parallel resonant
crystal and were chosen to minimize the ppm error.
Capacitor values can be adjusted slightly for different board
layouts to optimize accuracy.
Figure 8. Power Supply Filtering
3.3 V
0.01 F
0.01 F
10 F
10
V
CC
V
CCA
Figure 9. Crystal Input Interface
C1
33 pF
X1
18 pF
C2
27 pF
Parallel Crystal
X
OUT
X
IN
APPLICATION SCHEMATIC
Figure 10 shows a schematic example of the NB3N3001.
An example of LVPECL termination is shown in this
schematic. Additional LVPECL termination approaches are
shown in the AND8020 Application Note. In this example,
an 18 pF parallel resonant 26.5625MHz crystal is used for
generating 106.25 MHz output frequency. The C1 = 27 pF
and C2 = 33 pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 values may be
slightly adjusted for optimizing frequency accuracy.
Figure 10. Typical Application Schematic
R2
10
33 pF
R6
82.5
+
U1
1
2
3
4
8
7
6
5
R3
133
X1
Q
C5
0.1
C4
0.01 F
C1
27 pF
R5
133
V
CCA
V
EE
X
OUT
X
IN
V
CC
Z
O
= 50
Z
O
= 50
R4
82.5
V
CC
18 pF
C3
10 F
V
CC
V
CCA
C2
Q
Q
FSEL
Q
V
CC
V
CC
= 3.3 V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB3N3001DTG | 功能描述:時鐘合成器/抖動清除器 XTAL LVPECL FIBR CLK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| NB3N3001DTR2G | 功能描述:時鐘合成器/抖動清除器 XTAL LVPECL FIBR CLK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| NB3N3002 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V, Crystal-to-HCSL Clock Generator |
| NB3N3002DTG | 功能描述:鎖相環(huán) - PLL CLK GEN LVPECL DIFF OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NB3N3002DTR2G | 功能描述:鎖相環(huán) - PLL CLK GEN LVPECL DIFF OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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