參數(shù)資料
型號： NANDB9R4N2CZBA5E
廠商： NUMONYX
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA149
封裝： 10 X 13.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-149
文件頁數(shù)： 18/52頁
文件大小： 1126K
代理商： NANDB9R4N2CZBA5E
NANDxxxxNx
Signal descriptions
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2
Signal descriptions
See Figure 1, Figure 2, Figure 3, Figure 4, and Table 3 for a brief overview of the signals
connected to this device. The following sections further describe the signals.
For additional details on the signals, refer to the NAND flash memory and the LPSDRAM
datasheets.
2.1
Flash memory inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used by the NAND flash memory to input the selected address,
output the data during a read operation, or input a command or data during a write
operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left
floating when the NAND flash memory is deselected or the outputs are disabled.
2.2
Flash memory inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 NAND flash devices. They are used to output
the data during a read operation or input data during a write operation. Command and
address inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
2.3
Flash memory Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface of the NAND flash memory. When AL is High, the inputs are latched on the rising
edge of Write Enable.
2.4
Flash memory Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
Interface of the NAND flash memory. When CL is high, the inputs are latched on the rising
edge of Write Enable.
2.5
Flash memory Chip Enable (EF)
The NAND flash memory Chip Enable input activates the memory control logic, input
buffers, decoders, and sense amplifiers. When Chip Enable is Low, VIL, the NAND flash
memory device is selected. If Chip Enable goes High, vIH, while the NAND flash memory is
busy, the device remains selected and does not go into standby mode.
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