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參數(shù)資料
| 型號(hào)： | NAND16GW3B4DN6E |
| 廠商： | NUMONYX |
| 元件分類(lèi)： | PROM |
| 英文描述： | 4G X 4 FLASH 3V PROM, 25 ns, PDSO48 |
| 封裝： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 399K |
| 代理商： | NAND16GW3B4DN6E |
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NAND16GW3B4D
Signal descriptions
11/17
3.7
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, VIL, the device does not accept any
program or erase operations.
It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
3.8
Ready/Busy (RB1, RB2)
The Ready/Busy output, RB1 and RB2, is an open-drain output that can identify if the P/E/R
controller is currently active.
When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the
operation completes, Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low indicates that one, or more, of the memories is
busy.
During power-up and power-down a minimum recovery time of 10 s is required before the
command interface is ready to accept a command. During this period the Ready/Busy signal
is Low, VOL.
Refer to Section 6: Package mechanical for details on how to calculate the value of the pull-
up resistor.
3.9
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for operations (read, program, and erase).
An internal voltage detector disables all functions whenever VDD is below VLKO to protect the
device from any involuntary program/erase during power-transitions.
Each device in a system should have VDD decoupled with a 0.1 F capacitor. The PCB track
widths should be sufficient to carry the required program and erase currents.
3.10
VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
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