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參數(shù)資料
| 型號(hào)： | NAND16GW3B4DN6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4G X 4 FLASH 3V PROM, 25 ns, PDSO48 |
| 封裝： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 399K |
| 代理商： | NAND16GW3B4DN6E |
NAND16GW3B4D
Memory array organization
2
Memory array organization
The memory array is split into two dice. Each dice is comprised of NAND structures where
32 cells are connected in series.
The array is organized into blocks, where each block contains 64 pages. The array is split
into two areas: the main area and the spare area. The main area of the array stores data,
whereas the spare area typically stores software flags or bad block identification.
The pages are split into a 2048-byte main area and a spare area of 64 bytes.
2.1
Bad blocks
The NAND16GW3B4D device may contain bad blocks, where the reliability of blocks that
contain one or more invalid bits is not guaranteed. Additional bad blocks may develop during
the lifetime of the device.
The bad block information is written prior to shipping (refer to the bad block management
section of the NAND04G-B2D_NAND08G-BxC datasheet for more details).
Table 3: Valid blocks shows the minimum number of valid blocks. The values shown include
both the bad blocks that are present when the device is shipped and the bad blocks that
could develop later on. Each 8-Gbit device can have the same maximum number of bad
blocks.
These blocks need to be managed using bad blocks management and block replacement
(refer to the software algorithms section of the NAND04G-B2D_NAND08G-BxC datasheet).
2.2
Parallel operation
The NAND16GW3B4D is composed of two 8-Gbit devices, each one driven by its Chip
Enable pin (E1 and E2, respectively). It is possible to drive the two 8-Gbit devices in parallel,
thus increasing the throughput in Mbyte/s.
When one of the two devices is in a busy state, other operations can be issued on the other
available device.
Table 3.
Valid blocks
Density of device
Minimum
Maximum
16 Gbits
16064
16384
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