參數(shù)資料
型號: NAND16GW3B4DN6E
廠商: NUMONYX
元件分類: PROM
英文描述: 4G X 4 FLASH 3V PROM, 25 ns, PDSO48
封裝: 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù): 2/17頁
文件大小: 399K
代理商: NAND16GW3B4DN6E
Signal descriptions
NAND16GW3B4D
3
Signal descriptions
the signals connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address, output the data during a read
operation, or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.3
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
3.4
Chip Enable (E1, E2)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, VIL, the device is selected. If Chip Enable goes
High, VIH, while the device is busy, the device remains selected and does not go into
standby mode.
3.5
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
3.6
Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address, and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 s (min) is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
High during the recovery time.
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