參數(shù)資料
型號: NAND128W4A2CZA6E
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 8M X 16 FLASH 3V PROM, 35 ns, PBGA55
封裝: 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55
文件頁數(shù): 17/56頁
文件大?。?/td> 1209K
代理商: NAND128W4A2CZA6E
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
24/56
Page Program
The Page Program operation is the standard oper-
ation to program data to the memory array.
The main area of the memory array is pro-
grammed by page, however partial page program-
ming is allowed where any number of bytes (1 to
528) or words (1 to 264) can be programmed.
The maximum number of consecutive partial page
program operations allowed in the same page is
three. After exceeding this a Block Erase com-
mand must be issued before any further program
operations can take place in that page.
Before starting a Page Program operation a Point-
er operation can be performed to point to the area
to be programmed. Refer to the Pointer Opera-
tions section and Figure 12. for details.
Each Page Program operation consists of five
steps (see Figure 15.):
1.
one bus cycle is required to setup the Page
Program command
2.
four bus cycles are then required to input the
program address (refer to Table 6.)
3.
the data is then input (up to 528 Bytes/ 264
Words) and loaded into the Page Buffer
4.
one bus cycle is required to issue the confirm
command to start the P/E/R Controller.
5.
The P/E/R Controller then programs the data
into the array.
Once the program operation has started the Sta-
tus Register can be read using the Read Status
Register command. During program operations
the Status Register will only flag errors for bits set
to '1' that have not been successfully programmed
to '0'.
During the program operation, only the Read Sta-
tus Register and Reset commands will be accept-
ed, all other commands will be ignored.
Once the program operation has completed the P/
E/R Controller bit SR6 is set to ‘1’ and the Ready/
Busy signal goes High.
The device remains in Read Status Register mode
until another valid command is written to the Com-
mand Interface.
Figure 15. Page Program Operation
Note: Before starting a Page Program operation a Pointer operation can be performed. Refer to Pointer Operations section for details.
I/O
RB
Address Inputs
SR0
ai07566
Data Input
10h
70h
80h
Page Program
Setup Code
Confirm
Code
Read Status Register
Busy
tBLBH2
(Program Busy time)
相關(guān)PDF資料
PDF描述
NAND128R4A2BZA6E 8M X 16 FLASH 1.8V PROM, 35 ns, PBGA55
NAND256R4A0DN6T 16M X 16 FLASH 1.8V PROM, 15000 ns, PDSO48
NAND256R4A2DZA1F 16M X 16 FLASH 1.8V PROM, 15000 ns, PBGA63
NAND256W3A1BZA1E 32M X 8 FLASH 3V PROM, 12000 ns, PBGA63
NAND256W3A1DN1F 32M X 8 FLASH 3V PROM, 12000 ns, PDSO48
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