參數(shù)資料
型號: NAND128W4A2CZA6E
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 8M X 16 FLASH 3V PROM, 35 ns, PBGA55
封裝: 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55
文件頁數(shù): 15/56頁
文件大?。?/td> 1209K
代理商: NAND128W4A2CZA6E
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
22/56
Read Memory Array
Each operation to read the memory area starts
with a pointer operation as shown in the Pointer
Operations section. Once the area (main or spare)
has been selected using the Read A, Read B or
Read C commands four bus cycles (for 512Mb
and 1Gb devices) or three bus cycles (for 128Mb
and 256Mb devices) are required to input the ad-
dress (refer to Table 6.) of the data to be read.
The device defaults to Read A mode after power-
up or a Reset operation.
When reading the spare area addresses:
A0 to A3 (x8 devices)
A0 to A2 (x16 devices)
are used to set the start address of the spare area
while addresses:
A4 to A7 (x8 devices)
A3 to A7 (x16 devices)
are ignored.
Once the Read A or Read C commands have
been issued they do not need to be reissued for
subsequent read operations as the pointer re-
mains in the respective area. However, the Read
B command is effective for only one operation,
once an operation has been executed in Area B
the pointer returns automatically to Area A and so
another Read B command is required to start an-
other read operation in Area B.
Once a read command is issued two types of op-
erations are available: Random Read and Page
Read.
Random Read. Each time the command is is-
sued the first read is Random Read.
Page Read. After the Random Read access the
page data is transferred to the Page Buffer in a
time of tWHBH (refer to Table 21. for value). Once
the transfer is complete the Ready/Busy signal
goes High. The data can then be read out sequen-
tially (from selected column address to last column
address) by pulsing the Read Enable signal.
Figure 13. Read (A,B,C) Operations
CL
E
W
AL
R
I/O
RB
00h/
01h/ 50h
ai07595c
Busy
Command
Code
Address Input
Data Output (sequentially)
tBLBH1
(read)
相關(guān)PDF資料
PDF描述
NAND128R4A2BZA6E 8M X 16 FLASH 1.8V PROM, 35 ns, PBGA55
NAND256R4A0DN6T 16M X 16 FLASH 1.8V PROM, 15000 ns, PDSO48
NAND256R4A2DZA1F 16M X 16 FLASH 1.8V PROM, 15000 ns, PBGA63
NAND256W3A1BZA1E 32M X 8 FLASH 3V PROM, 12000 ns, PBGA63
NAND256W3A1DN1F 32M X 8 FLASH 3V PROM, 12000 ns, PDSO48
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