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參數(shù)資料
| 型號： | NAND02GW3B3BZB1F |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 256M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| 封裝： | 9.50 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-63 |
| 文件頁數(shù)： | 20/59頁 |
| 文件大?。?/td> | 998K |
| 代理商： | NAND02GW3B3BZB1F |
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Block Erase
Erase operations are done one block at a time. An
erase operation sets all of the bits in the ad-
dressed block to ‘1’. All previous data in the block
is lost.
An erase operation consists of three steps (refer to
1.
One bus cycle is required to setup the Block
Erase command. Only addresses A18-A27
(x8) or A17-A26 (x16) are used, the other
address inputs are ignored.
2.
two or three bus cycles are then required to
load the address of the block to be erased.
addresses of each device.
3.
one bus cycle is required to issue the Block
Erase confirm command to start the P/E/R
Controller.
The operation is initiated on the rising edge of
write Enable, W, after the confirm command is is-
sued. The P/E/R Controller handles Block Erase
and implements the verify process.
During the Block Erase operation, only the Read
Status Register and Reset commands will be ac-
cepted, all other commands will be ignored.
Once the program operation has completed the P/
E/R Controller bit SR6 is set to ‘1’ and the Ready/
Busy signal goes High. If the operation completed
successfully, the Write Status Bit SR0 is ‘0’, other-
wise it is set to ‘1’.
Figure 17. Block Erase Operation
Reset
The Reset command is used to reset the Com-
mand Interface and Status Register. If the Reset
command is issued during any operation, the op-
eration will be aborted. If it was a program or erase
operation that was aborted, the contents of the
memory locations being modified will no longer be
valid as the data will be partially programmed or
erased.
If the device has already been reset then the new
Reset command will not be accepted.
The Ready/Busy signal goes Low for tBLBH4 after
the Reset command is issued. The value of tBLBH4
depends on the operation that the device was per-
forming when the command was issued, refer to
Table 25. for the values.
I/O
RB
Block Address
Inputs
SR0
ai07593
D0h
70h
60h
Block Erase
Setup Code
Confirm
Code
Read Status Register
Busy
tBLBH3
(Erase Busy time)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NAND02GW3B3BN1F | 256M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND02GW3B3CN6 | 256M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND04GR3B3BN1F | 512M X 8 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND512W3B3BN1E | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND512W3B3CN6E | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND04GR3B2DDI6 | 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film |
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