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參數(shù)資料
| 型號： | MX803A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Audio Signaling Processor |
| 中文描述： | 音頻信號處理器 |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 225K |
| 代理商： | MX803A |
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Audio Signaling Processor
20
MX803A PRELIMINARY INFORMATION
1996 MX
COM, INC.
Tele: 800 638 5577 910 744 5050 Fax: 910 744 5054
Doc. # 20480122.003
5.6 General Reset
Upon power-up the bits in the MX803A registers will be random (either “0” or “1”). A General Reset Command (01
H
) will
be required to reset all microcircuits on the C-BUS. It has the following effect on the MX803A:
Control Register
Status Register (bits 0, 1, 2)
Notone Timer
Tone Gen. 1 Reg. (2 bytes)
Tone Gen. 2 Reg. (2 bytes)
Gen. Purpose Reg.
Set as 00
H
Set as 00
H
Set as 00
H
Set as 0000
H
Set as 0000
H
Set as 00
H
Table 10: General Reset effect on MX803A
This sets the MX803A to Encoder High Band (625Hz to 3000Hz) with interrupts disabled and both timers set to 00
H
.
Both timers should be set up before interrupts are enabled to prevent initial, undesired interrupts.
6. Timing Information
Figure 8 shows timing parameters for two-way communication between the
μ
C and the MX803A on the C-BUS.
CHIP
SELECT
SERIAL
CLOCK
COMMAND
DATA
REPLY
DATA
ADDRESS/COMMAND
BYTE
FIRST
DATA
BYTE
LAST
DATA
BYTE
FIRST
REPLY
DATA
BYTE
LAST
REPLY
DATA
BYTE
Logic
level
is
not
important
MSB
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
t
CSOFF
t
CK
t
NXT
t
HIZ
t
CSE
t
NXT
t
NXT
Figure 8: C-BUS Timing
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相關(guān)代理商/技術(shù)參數(shù) |
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| MX803ADW | 制造商:CML Innovative Technologies 功能描述:Audio Signalling Processor, Tube |
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| MX803ALH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio Signaling Processor |
| MX803J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF/Baseband Circuit |
| MX803LH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF/Baseband Circuit |
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