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參數(shù)資料
| 型號： | MX803A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Audio Signaling Processor |
| 中文描述： | 音頻信號處理器 |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 225K |
| 代理商： | MX803A |
Audio Signaling Processor
11
MX803A PRELIMINARY INFORMATION
1996 MX
COM, INC.
Tele: 800 638 5577 910 744 5050 Fax: 910 744 5054
Doc. # 20480122.003
5.2.2 Read Status Register
A/C 31
H
, followed by 1 byte of Reply Data
Interrupt Requests (IRQ):
Interrupts on this device are available to draw the attention of the
μ
C to a change in the
condition of the bit in the status register. However, bits are set in the status register irrespective of the setting of interrupt
enable bits (Table 2) and these changes may be recognized by polling the register.
General Purpose Timer Period:
Set to a logic “1” when the timer period has expired. Cleared to a logic “0” by:
1. Reading the Status Register
2. New G/Purpose Timer information
3. General Reset command
Notone Timer Period:
Set to a logic “1” when the timer period has expired. Cleared to a logic “0” by:
1. Reading the Status Register
2. New Notone Timer information
3. General Reset command
RX Tone Measurement:
Set to a logic “1” when the RX Tone Measurement is complete. Cleared to a logic “0” by:
1. Reading the Status Register
2. General Reset command
Setting
MSB
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
1
0
Bit 2
1
Status Bits
Received First
Set to
0
Set to
0
Set to
0
Set to
0
Logic Input Status
1
0
G/Purpose Timer Period
Expired
(Interrupt Generated)
Notone Timer Period
Expired
(Interrupt Generated)
RX Tone Measurement
Complete
(Interrupt Generated)
Bit 1
1
Bit 0
1
Table 3: Status Register
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| MX803ADW | 制造商:CML Innovative Technologies 功能描述:Audio Signalling Processor, Tube |
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| MX803ALH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio Signaling Processor |
| MX803J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RF/Baseband Circuit |
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