參數(shù)資料
型號(hào)： MX29F1611
廠商： Electronic Theatre Controls, Inc.
英文描述： 16M-BIT [2M x 8/1M x 16] CMOS SINGLE VOLTAGE PAGEMODE FLASH EEPROM
中文描述： 1,600位[2米x 8/1M × 16] CMOS單電壓閃存EEPROM PAGEMODE
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 171K
代理商： MX29F1611
14
P/N: PM0440
REV. 1.6, JUL. 16, 1998
MX29F1611
ABORT MODE
To activate Abort mode, a three-bus cycle operation is
required. The E0H command (Refer to table 3) only stops
Page program or Sector /Chip erase operation currently
in progress and puts the device in Sleep mode. But unlike
the sleep command, the program or erase operation will
not be completed. Since the data in some page/sectors
is no longer valid due to an incomplete program or erase
operation, the program fail (DQ4) or erase fail (DQ5)bit
will be set.
After the abort command is executed and with CMOS
input level applied, the device current is reduced to the
same level as in sleep modes.
During Abort mode, the status registers, Silicon ID codes
remain valid and can still be read. The Device Sleep
Status bit - DQ2 will indicate that the device in the sleep
mode.
Similar to the sleep mode, A read array command MUST
be written to bring the device out of the abort state without
incurring any wake up latency. Note that once device is
waken up, Clear status register mode is required before
a program or erase operation can be executed.
DATA PROTECTION
The MX29F1611 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the Read Array mode.
Also, with its control register architecture, alteration of the
memory contents only occurs after successful
completion of specific multi-bus cycle command
sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up
and power-down, a write cycle is locked out for VCC less
than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the
command register is disabled and all internal program/
erase circuits are disabled. Under this condition the
device will reset to the read mode. Subsequent writes will
be ignored until the VCC level is greater than VLKO. It is
the user's responsibility to ensure that the control pins are
logically correct to prevent unintentional write when VCC
is above VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
INDEX
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