- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385641 > MT9LD272AG (Micron Technology, Inc.) 2Meg x 72 Nonbuffered DRAM DIMMs(2M x 72無緩沖動態(tài)RAM雙列直插存儲器模塊) PDF資料下載
參數(shù)資料
| 型號： | MT9LD272AG |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2Meg x 72 Nonbuffered DRAM DIMMs(2M x 72無緩沖動態(tài)RAM雙列直插存儲器模塊) |
| 中文描述： | 2Meg × 72 Nonbuffered內(nèi)存插槽（200萬× 72無緩沖動態(tài)RAM的雙列直插存儲器模塊） |
| 文件頁數(shù)： | 15/30頁 |
| 文件大小： | 410K |
| 代理商： | MT9LD272AG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
15
2, 4 MEG x 72
NONBUFFERED DRAM DIMMs
OBSOLETE
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
DD
= +3.3V; f = 1 MHz.
3. I
CC
is dependent on output loading. Specified values
are obtained with minimum cycle time and the
outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is ensured.
6. An initial pause of 100
μ
s is required after power-up,
followed by eight RAS# REFRESH cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the
t
REF refresh
requirement is exceeded.
7. AC characteristics assume
t
T = 5ns for FPM and 2.5ns
for EDO.
8. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
9. In addition to meeting the transition rate specifica-
tion, all input signals must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
10. If CAS# = V
IH
, data output is High-Z.
11. If CAS# = V
IL
, data output may contain data from the
last valid READ cycle.
12. Measured with a load equivalent to two TTL gates
and 100pF and V
OL
= 0.8V and V
OH
= 2V.
13. Requires that
t
AA and
t
RAC are not violated.
14. Requires that
t
AA and
t
CAC are not violated.
15. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for
t
CP.
16. The
t
RCD (MAX) limit is no longer specified.
t
RCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
t
RCD (MAX)
limit, then access time was controlled exclusively by
t
CAC (
t
RAC [MIN] no longer applied). With or
without the
t
RCD (MAX) limit,
t
AA and
t
CAC must
always be met.
17. The
t
RAD (MAX) limit is no longer specified.
t
RAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified
t
RAD (MAX)
limit, then access time was controlled exclusively by
t
AA (
t
RAC and
t
CAC no longer applied). With or
without the
t
RAD (MAX) limit,
t
AA,
t
RAC and
t
CAC
must always be met.
18. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
19.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
20. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21. LATE WRITE and READ-MODIFY-WRITE cycles
must have both
t
OD and
t
OEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW after
t
OEH is met. If CAS# goes HIGH prior to OE# going
back LOW, the DQs will remain open.
22. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
23.
t
WCS,
t
RWD,
t
AWD and
t
CWD are not restrictive
operating parameters.
t
WCS applies to EARLY
WRITE cycles.
t
RWD,
t
AWD and
t
CWD apply to
READ-MODIFY-WRITE cycles. If
t
WCS
≥
t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If
t
WCS <
t
WSC (MIN) and
t
RWD
≥
t
RWD (MIN),
t
AWD
≥
t
AWD (MIN) and
t
CWD
≥
t
CWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle.
t
WCS,
t
RWD,
t
CWD and
t
AWD are not applicable in a LATE
WRITE cycle.
24. Column address changed once each cycle.
25. The 3ns minimum parameter guaranteed by design.
26. With the FPM option,
t
OFF is determined by the first
RAS# or CAS# signal to transition HIGH. In compari-
son,
t
OFF on an EDO option is determined by the
latter of the RAS# and CAS# signals to transition
HIGH.
27. Applies to both FPM and EDO modules.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9LD272 | 2Meg x 72 Buffered DRAM DIMMs(2M x 72緩沖動態(tài)RAM模塊（雙列直插存儲器模塊）) |
| MT9VDDT1672A | DDR SDRAM DIMM |
| MT9VDDT3272A | DDR SDRAM DIMM |
| MTB2P50E | Power MOSFET 2 Amps, 500 Volts(2A, 500V功率MOSFET) |
| MTB50P03HDL | Power MOSFET 50 Amps, 30 Volts, Logic Level(50A, 30V, D2PAK, P溝道功率MOSFET) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9LD272AG-52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
| MT9LD272AG-5X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| MT9LD272AG-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Fast Page Mode DRAM Module |
| MT9LD272AG-60B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 Burst EDO Page Mode DRAM Module |
| MT9LD272AG-6X | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:2, 4 MEG x 72 NONBUFFERED DRAM DIMMs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。