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參數(shù)資料
| 型號(hào)： | MT92101 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IP Phone Processor(IP電話處理器（提供一個(gè)用于企業(yè)IP電話的解決方案）) |
| 中文描述： | IP電話處理器（的IP電話處理器（提供一個(gè)用于企業(yè)的IP電話的解決方案）） |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | MT92101 |
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Preliminary Information
MT92101
9
twice the rate of the CPU (or greater) to guarantee
correct operation.
Power Control
The Power Control block allows selection of power
states (enabled or disabled) for each CPU
subsystem peripheral during STANDBY and RUN
power modes. All CPU subsystem peripherals may
be powered down in this way, although some core
activity remains in the key blocks (External Memory
Interface, B
μ
ILD Broadcast Module, Watchdog
Timer, and within this block). The Power Control
block also contains a control bit to allow selection of
STANDBY mode.
B
μ
ILD Broadcast Module
The B
μ
ILD Broadcast Module block performs a
number of functions essential to operation of the
B
us
for
μ
Controller
I
ntegration in
L
ow-power
D
esigns
(B
μ
ILD).
bus master arbitration,
control of bus modes,
hardware system debug support and diagnostic
generation,
stores system configuration data,
handshaking to allow external bus masterhip.
System configuration data includes clock selection,
PLL programming, bus master prioritization and
DMA assignment.
External bus masters are supported via a simple
two-pin handshaking mechanism. Upon granting
external bus mastership, all the external memory
interface pins (address, data, chip select and
enables) are tri-stated. The external bus master may
then access any external memory or other peripheral
devices. However, the interface does not support
external bus master accesses of on-chip memory or
peripherals.
Boot ROM
Application boot normally runs directly from external
ROM/FLASH at location 0x00000000. Alternatively, if
pin GPIO[0] is held low on exit from system reset,
boot occurs from the internal boot ROM (FLASH
Load Mode). The internal ROM contains a simple
algorithm to allow download and execution of a user-
defined program directly from the UART. Typically
during a FLASH Load, this program will download full
application code via the UART and program it into
the on-board FLASH ROM during end product
manufacture or field re-program. Alternatively, in
situations where full debug tools are not appropriate,
test software could be downloaded.
CPU Memory Map
Address space is split into 8 equal segments,
decoded from the top 3 address lines. The bottom 6
segments form the main memory areas for the
internal Boot ROM and the 5 external memory areas.
The next segment is reserved and the final area is
used for all internal memory mapped registers. This
final segment is further subdivided into sub-
segments, each of 1024 Words, with all memory-
mapped blocks being allocated one sub-segment.
Table 1. CPU Subsystem Memory Mapped
Registers
Further details of this allocation and of all register
bits are described in a separate publication,
MT92101 IP Phone Processor Handbook, DM5252.
Each main memory area may address up to 512
Mbytes (ADDR[28:0]). However, this is limited to just
4Mbytes (ADDR[21:0]), due to the number of
address pins available on the MT92101. Any attempt
to access memory outside of this range will access
copied images of the 4Mbyte areas.
Reserved, Test Access Only
0xE0030000
→
0xE03FFFF
Ethernet MAC 2
0xE002 E000
→
EFFF
0xE002 D000
→
DFFF
0xE002 C000
→
CFFF
0xE002 A000
→
AFFF
0xE002 9000
→
9FFF
0xE002 7000
→
7FFF
0xE002 6000
→
6FFF
0xE002 5000
→
5FFF
0xE002 4000
→
4FFF
0xE002 0000
→
0FFF
0xE001 C000
→
CFFF
0xE001 8000
→
8FFF
0xE000 D000
→
DFFF
0xE000 C000
→
CFFF
0xE000 8000
→
8FFF
0xE000 6000
→
6FFF
0xE000 5000
→
5FFF
0xE000 4000
→
4FFF
0xE000 2000
→
2FFF
0xE000 0000
→
0FFF
Ethernet MAC 1
802.1 Ethernet Bridge
USB Device Interface
Programmable Key Module
Synchronous Serial Interface
General Purpose Timer
Keypad Scanner
General Purpose IO
Memory Interface (AOI)
TDM Master SIO
UART
DMAC 2
DMAC 1
External Memory Interface
Interrupt Controller
Power Control
Watchdog Timer
BuILD Broadcast Module
Reserved, Test Access Only
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