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參數(shù)資料
| 型號(hào)： | MT92101 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IP Phone Processor(IP電話處理器（提供一個(gè)用于企業(yè)IP電話的解決方案）) |
| 中文描述： | IP電話處理器（的IP電話處理器（提供一個(gè)用于企業(yè)的IP電話的解決方案）） |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大小： | 174K |
| 代理商： | MT92101 |
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Preliminary Information
MT92101
13
The DSP subsystem clock is generated from MCLK
or UCLK via a fully embedded programmable PLL
(n*0.25*CLK, up to 90MHz). It is generated through a
programmable divide by 1 / 2 / 4, followed by a fully
programmable PLL giving integer multiplication. A
further programmable divide by 1 / 2 stage after the
PLL allows further flexibility. Clock source selection
for the PLL is programmable by the CPU, although
the default is to MCLK. Changes to this clock source
may only be made while the DSP subsystem is in
STOP mode. When active, the DSP clock must
always operate at least twice as fast as the CPU
clock to allow correct operation of the AOI block. See
Figure 3 for an illustration.
The reset pin, nRESET, utilises a power-on-reset
cell, which may be used as the source of a reset for
other devices. A single external component (a
capacitor) is required to provide the appropriate time
constant.
Embedded DSP Firmware
The OAK subsystem has embedded full physical
layer
firmware,
including
compression, acoustic functions and a host interface.
multi-channel
voice
Multiple simultaneous voice channels can be
supported, up to the 90 DSP MIP limit, dependent
upon voice compression and audio echo cancellation
requirements.
Acoustic functions supported include DTMF/call
progress tone generation, acoustic echo cancellation,
volume control and sidetone generation.
The host interface provides a communications link
between the DSP subsystem and the controlling
CPU. All information passed between the two
processors is processed by this module.
All firmware modules are run within a simple RTOS
that handles all scheduling and prioritising of tasks
and maximises usage of available DSP MIPS. All
firmware modules have been extensively verified
using a combination of software simulation and
hardware emulation.
Firmware Feature List
The following features are supported in firmware:
G.729.AB compression;
G.723.1A compression;
Figure 3 - Clock Provision, Multiplexing and Division/Multiplication
Master Clock
MCLK
USB Clock
UCLK
CPU Subsystem
Clock
DSP Subsystem Clock
TDM Clock
10 MHz
48 MHz
10 MHz (MCLK)
56.25 MHz (9 * ECLK / 4)
1 MHz (MCLK / 10)
24.576
48
24.576 (MCLK)
60MHz (6 * MCLK)
2.048 (MCLK / 12)
40.96
48
40.96 (MCLK)
81.92 (2 * MCLK)
4.096 (MCLK / 10)
40
48
2.5 (MCLK / 16)
Table 5 - Example Clock Configurations
STOP
External - Inactive
OSC
OSC
USBOSCDIS
Note: All configuration via System Configuration Register
DIV
1/2/4/8/16
MUX
DIV 1/2/4
PLL
*1 TO *23
DIV 1/2
CPU Subsystem Clock
To TDM Interfaces
(Division to Generate
TDM Clocks)
DSP
Subsystem
Clock
ARMCLKDIV
OAKCLKSRC
OAKCLKDIV
OAKCLKMPY
DSP Subsystem STOP
Exit Time Clock
OAKPLLDIV
USB Clock (48.00MHz)
MCLK
MCLKO
UCLKO
UCLK
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