
MT92101
Preliminary Information
14
VAD / CNG;
audio echo suppression;
DTMF / call progress tone detection and
generation;
sidetone and loopback;
caller ID in-band signalling generation;
adaptive playout;
signal classifier;
executive/RTOS.
CPU Software
Full software is provided for demonstration purposes
and as the basis for a full system. The H.323, SIP
and MGCP/MEGACO protocol stacks, if required,
are available only as object code and have an
associated per-use license cost.
All software modules have been verified and are
believed to support full interoperability with existing
equipment. However, full independent verification/
approval of this software has not yet been achieved.
Software Feature List
The following features are available as software
modules:
protocol stacks: H.323, SIP and MGCP/
MEGACO;
RTP/RTCP transport layer;
interface API to the DSP subsystem;
reference phone application, including a basic
MMI;
BSP and hardware drivers associated with all of
the above;
standard RTOS support for Precise/MQX from
Precise Software Technologies Inc.
Alternative
supported, dependant upon customer requirements.
Possibilities include pSOS from Integrated Systems
Inc., Nucleus from Accelerated Technology Inc., and
VxWorks from Wind River Systems.
operating
systems
may
also
be
Technology and Packaging
The MT92101 is realised in our well proven 0.35
μ
m
triple layer metal CMOS technology, for earliest
availability of prototypes at minimum risk. This part
supports audio echo cancellation only as a firmware
upgrade to the DSP, and operates at maximum clock
speeds of 25MHz for the CPU subsystem and
60MHz (MIPs) for the DSP subsystem. DSP access
to external memory over the C-bus can reach
40MHz, dependant upon memory speed. It is
available in 208 pin TQFP, 28 x 28 x 1.4 mm, 0.5mm
pitch, or in 288 ball (238 used ball) PBGA, 23 x 23 x
1.2mm, 1mm pitch, package options.
A
development devices only. These development
devices use all connections on the above PBGA
package to provide access to the DSP combined
program and data buses (C-bus), to allow full DSP
debug and operation with external DSP memory.
further
package
option
is
supported
for
Next Generation Realisation on 0.18
μ
m
Technology, MT92102
The MT92102 will be realised in a very small
geometry, 0.18
μ
m, quad layer metal CMOS
technology for lowest cost and power consumption
and
supports
all
features
performance
outlined
MT92102 will support fully audio echo cancellation,
and will operate at greater maximum clock speeds.
and
Additionally,
parametric
here.
the
The MT92102 will be fully pin compatible with the
MT92101, although it will be necessary to supply two
power supply voltages. The development device for
the MT92102 will have the ability to use external
program memory - zero-wait at up to about 50MHz,
dependant upon memory speed, is included.
Development Support
The MT92101 is supported with a development/
evaluation kit which includes two evaluation boards
and a comprehensive suite of software APIs,
development tools and PC-based exercisers to allow
the rapid development of IP phone applications,
SOHO gateways and similar applications. The kit will
also support the MT92102. The boards support full
CPU debug access and basic DSP debug access via
a JTAG interface. Full DSP debug access may be
provided optionally via a C-bus interface.
H.323 Development Toolkit
An optional add-on software toolkit is available to
provide a full complement of H.323, including H.235
and H.450 extensions.
MGCP/MEGACO and SIP
Development toolkits for SIP and MGCP/MEGACO
will be available shortly.