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參數(shù)資料
| 型號： | MT92101 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IP Phone Processor(IP電話處理器（提供一個用于企業(yè)IP電話的解決方案）) |
| 中文描述： | IP電話處理器（的IP電話處理器（提供一個用于企業(yè)的IP電話的解決方案）） |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 174K |
| 代理商： | MT92101 |
Preliminary Information
MT92101
15
Absolute Maximum Ratings*
- Voltages are with respect to ground (GND) unless otherwise stated.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions
Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.
Typical figures are at 25
°
C with nominal VDD + VIO and are for design aid only.
a. MT92102 will have an additional 1.8V nominal power supply.
Electrical Characteristics
Parameter
Symbol
Min
Max
Units
1
Any VDD Pin to any GND Pin
- 0.3
2.5
V
2
Any Signal Pin to GND
- 0.3
VDD + 0.5
V
3
Storage Temperature Range
- 55
125
C
4
ESD
2
2
kV
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
1
Operating voltage range
a
VDD
3.0
3.3
3.6
V
Chip core power supply
2
Operating temperature range
OT
-40
+85
C
3
Input high voltage
VIH
0.7*VDD
V
4
Input low voltage
VIL
0.3*VDD
V
5
Input pull-up/down current
IIPU/IIPD
33
90
μ
A
μ
A
0 < VIN < 3.6
6
Input current
II
5
0 < VIN < 3.6 All other inputs
7
Input capacitance
CIN
10
pF
All inputs and IO's
8
Output high voltage
VOH
0.8*VDD
V
|IOUT|=100 uA (microA)
9
Output low voltage
VOL
0.4*VDD
V
|IOUT|=100 uA (microA)
10 Three-state leakage current
IO
10
μ
A
All outputs and IO's
11 Output capacitance
COUT
40
pF
Total external load, all outputs
and IO's
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Clock input frequency
MCLK
25
MHz
CPU subsystem frequency
2
Clock input frequency
UCLK
48
60
MHz
Unity input ratio
3
Clock input ratio
MCLK
45:55
55:45
%
Digital input 25 MHz
4
Clock input ratio
UCLK
40:60
60:40
%
Digital input 48 MHz
5
Crystal load capacitance
12
30
pF
MCLK and UCLK
6
Crystal start time
400
mS
MCLK and UCLK
Power Consumption
7
MCLK = 25 MHz
UCLK disabled
0.8
mA
CPU Subsystem STANDBY
DSP Subsystem STOP
8
MCLK = 25 MHz , DSP
Subsystem clock = 60MHz
4
mA
CPU Subsystem STANDBY
DSP Subsystem IDLE
9
CPU Subsystem
0.5
mA per MHz
CPU Subsystem RUN
DSP Subsystem STOP
10
DSP Subsystem
1.0
mA per MIP
CPU Subsystem STANDBY
DSP Subsystem ACTIVE
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