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參數(shù)資料
| 型號： | MT92101 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IP Phone Processor(IP電話處理器（提供一個用于企業(yè)IP電話的解決方案）) |
| 中文描述： | IP電話處理器（的IP電話處理器（提供一個用于企業(yè)的IP電話的解決方案）） |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 174K |
| 代理商： | MT92101 |
Preliminary Information
MT92101
11
Memory Interface (AOI, or ARM-OAK Interface)
The AOI is the primary link between the CPU and
DSP subsystems and is described in the CPU
subsystem part of this datasheet (see page 8).
C-bus Interface
The C-bus interface is required to support full DSP
debug and is a 37-pin parallel interface giving access
to the combined (multiplexed) DSP data and
program busses. The C-bus interface is only
available on the development pinned device.
TDM Audio Serial Interface
The TDM Audio Serial Interface is used for
transferring audio data to one or more voice
CODECs or similar devices. The interface is
substantially identical to the TDM Master interface
within the CPU subsystem and is a fully flexible
multi-channel PCM based interface, which provides
the following:
a five pin interface (1 clock, RX and TX frame
syncs, input data and output data);
frame syncs and clock support programmable
direction and polarity;
single or multi-channel capability, allowing time
division multiplexing of the serial bitstream into
up to 32 channels; any number of these
channels can be used for transmit or receive
independently; the DSP must supply data for
the transmit channels in the correct order, and
sort data from the receive channel;
compatible with Mitel ST-Bus and most PCM
busses;
transmit and receive sections can operate with
DMA from/to memory to reduce DSP
interaction; the DMA controller can be
programmed with the number of Words to
transmit or receive (up to 8192 Words each)
and generates an interrupt when complete;
a compander circuit is included to support A-
law and
μ
-law interfaces. When enabled the
companding operation is transparent to the
DSP. The compander may also be accessed
independently by the DSP to allow separate
compression and expansion operations, in
parallel with companded or non-companded
serial IO.
Acoustic Echo Canceller (AEC)
The AEC is achieved through a firmware upgrade
and is a half-duplex DSP firmware solution. It
operates in conjunction with the TDM Audio Serial
Interface to cancel acoustic echo on a single,
programmable, audio channel.
Direct Memory Access Controller (DMAC)
The DMAC operates in conjunction with the TDM
Audio Interface and the AOI to allow data to be
transferred to or from the external voice CODECs
and DSP data memory, and to or from the CPU
subsystem (usually shared external memory) and
DSP data memory with no DSP intervention. The
hardware associated with this function is located in
the Bus Interface Unit and in the AOI.
Interrupt Controller
The Interrupt Controller block manages all internally
generated DSP subsystem interrupts, plus 2 external
interrupts
(sharing
INT[5:4]
interrupts). The controller translates these to one of
three interrupt priority levels to the OAKDSPCore
TM
in a fully programmable way. Inputs are edge
sensitive.
pins
with
CPU
Bus Interface Unit
The Bus Interface Unit (BIU) controls all access to
the on-chip DSP data and program busses. It
produces the C-bus and contains the DSP GPIO and
DMA circuitry. It allows individual selection of
external C-bus program, data, mailbox and monitor
program wait states. Power control for data
memories and peripherals is also managed from this
block.
DSP Memory Map
The DSP data space contains 7kWords of RAM (2-
kWord on-core XRAM, 2-kWord on-core YRAM and
3-kWord off-core XRAM) plus 8-kWords ROM for
storage of data tables and filter coefficients. Another
16-kWords is allocated to shared memory, 1-kWords
to an external emulation mailbox, 1-kWords to
external file IO and 4-kWords to memory mapped
registers. A 16-kWord window is available for
external C-bus access to support development. Each
memory-mapped block is assigned its own 256-Word
window.
The DSP program space contains 59-kWords of
application ROM plus 4-kWords of RAM to support
program patches and customisation. The remaining
1kWord is reserved for an external monitor program
to support emulation and debug. This program
memroy map is mirrored internally to allow an
internal monitor program to support enhanced debug
via the Memory Interface and JTAG port in the future.
All of this space, with the exception of boot code,
may be mapped to the C-bus for external
development use.
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