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參數(shù)資料
| 型號： | MT9171AE1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PDIP22 |
| 封裝： | LEAD FREE, PLASTIC, DIP-22 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 552K |
| 代理商： | MT9171AE1 |
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MT9171/72
Data Sheet
7
Zarlink Semiconductor Inc.
Figure 7 - CD Port (Modes 2,6)
Figure 8 - CD Port (Modes 1,5)
The composite transmit and receive signal is received at L
IN
.
On entering the DNIC this signal passes through a
Precanceller which is a summing amplifier and lowpass filter that partially cancels the near-end signal and provides
first order antialiasing for the received signal. Internal, partial cancellation of the near end signal may be disabled by
holding the Precan pin high. This mode simplifies the design of external line transceivers used for loop extension
applications. The Precan pin features an internal pull-down which allows this pin to be left unconnected in
applications where this function is not required. The resultant signal passes through a receive filter to bandlimit and
equalize it. At this point, the echo estimate from the echo canceller is subtracted from the precancelled received
signal. This difference signal is then input to the echo canceller as an error signal and also squared up by a
comparator and passed to the biphase receiver. Within the echo canceller, the sign of this error signal is
determined. Depending on the sign, the echo estimate is either incremented or decremented and this new estimate
is stored back in RAM.
The timebase in both SLV and MAS modes (generated internally in SLV mode and externally in MAS mode) is
phase-locked to the received data stream. This phase-locked clock operates the Biphase Decoder, Descrambler
and Deprescrambler in MAS mode and the entire chip in SLV mode. The Biphase Decoder decodes the received
encoded bit stream resulting in the original NRZ data which is passed onto the Descrambler and Deprescrambler
where the data is restored to its original content by performing the reverse polynomials. The SYNC bits are
F0
C4
CDSTo
CDSTi
F0o
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
C
0
C
0
3.9
μ
sec
62.5
μ
sec
125
μ
sec
Channel Time 0
Channel Time 16
CLD
TCK
CDi
CDo
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
6
C
7
C
0
C
1
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
6
C
7
C
0
C
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9171 | ISO2-CMOS ST-BUS FAMILY |
| MT9171AE | ISO2-CMOS ST-BUS FAMILY |
| MT9171AN | ISO2-CMOS ST-BUS FAMILY |
| MT9171AP | ISO2-CMOS ST-BUS FAMILY |
| MT9171 | ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9171AN | 制造商:Microsemi Corporation 功能描述: |
| MT9171AN1 | 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DNIC 1.5UM - Rail/Tube |
| MT9171ANR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| MT9171ANR1 | 制造商:Microsemi Corporation 功能描述:PB FREE DNIC 1.5MM - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DNIC 1.5MM - Tape and Reel |
| MT9171AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:ISO2-CMOS ST-BUS FAMILY |
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