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參數(shù)資料
| 型號(hào)： | MT9171AE1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PDIP22 |
| 封裝： | LEAD FREE, PLASTIC, DIP-22 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 552K |
| 代理商： | MT9171AE1 |
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MT9171/72
Data Sheet
13
Zarlink Semiconductor Inc.
Table 5 - Diagnostic Register
Notes:
1.
depending upon the status of bit-3.
2.
Do not use L
OUT
to L
IN
loopback in DN/SLV mode.
3.
Do not use DSTo to DSTi loopback in MOD/MAS mode.
When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,
The Diagnostics Register Reset bit (bit 2) of the Control Register determines the reset state of the Diagnostics
Register. If, on writing to the Control Register, this bit is set to logic “0”, the Diagnostics Register will be reset
coincident with the frame pulse. When this bit is logic “1”, the Diagnostics Register will not be reset. In order to use
the diagnostic features, the Diagnostics Register must be continuously written to. The output C-channel sends
status information from the Status Register to the system along with the received HK bit as shown in Table 6.
Table 6 - Status Register
4
FUN
1
Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC
recovery circuitry. When set to ’0’, the operation continues in synchronization.
5
PSWAP
1
Polynomial Swap. When set to ’1’, the scrambling and descrambling polynomials
are interchanged (use for MAS mode only). When set to ’0’, the polynomials retain
their normal designations.
6
DLO
1
Disable Line Out. When set to ’1’, the signal on L
OUT
is set to V
Bias
. When set to ’0’,
L
OUT
pin functions normally.
Must be set to ’0’ for normal operation.
7
Not Used
Status
Register
Name
Function
0
SYNC
Synchronization
- When set this bit indicates that synchronization to the received
line data sync pattern has been acquired. For DN mode only.
1-2
CHQual
Channel Quality -
These bits provide an estimate of the receiver’s margin against
noise. The farther this 2 bit value is from 0 the better the SNR.
3
Rx
HK
Housekeeping -
This bit is the received housekeeping (HK) bit from the far end.
4-6
Future
Future Functionality.
These bits return Logic 1 when read.
7
ID
This bit provides a hardware identifier for the DNIC revision. The MT9171/72 will
return a logic “0” for this bit. (Logic “1” returned for MT8972A.)
Bit
Name
Description
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Reg Sel-1
Reg Sel-2
Loopback
FUN
PSWAP
DLO
Not Used
Default Mode Selection
(Refer to Table 4a)
0
1
2
3
4
5
6
7
SYNC
CHQual
Rx HK
Future Functionality
ID
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9171 | ISO2-CMOS ST-BUS FAMILY |
| MT9171AE | ISO2-CMOS ST-BUS FAMILY |
| MT9171AN | ISO2-CMOS ST-BUS FAMILY |
| MT9171AP | ISO2-CMOS ST-BUS FAMILY |
| MT9171 | ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9171AN | 制造商:Microsemi Corporation 功能描述: |
| MT9171AN1 | 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DNIC 1.5UM - Rail/Tube |
| MT9171ANR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| MT9171ANR1 | 制造商:Microsemi Corporation 功能描述:PB FREE DNIC 1.5MM - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DNIC 1.5MM - Tape and Reel |
| MT9171AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:ISO2-CMOS ST-BUS FAMILY |
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