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參數(shù)資料
| 型號(hào)： | MT9171AE1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| 中文描述： | DATACOM, DIGITAL SLIC, PDIP22 |
| 封裝： | LEAD FREE, PLASTIC, DIP-22 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 552K |
| 代理商： | MT9171AE1 |
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MT9171/72
Data Sheet
16
Zarlink Semiconductor Inc.
Figure 12 - Frame Format - 160 kbit/s (Modes 0, 2, 3, 4, 6)
Applications
Typical connection diagrams are shown in Figures 13 and 14 for the DN mode as a MASTER and SLAVE,
respectively. L
OUT
is connected to the coupling transformer through a resistor R2 and capacitors C2 and C2’ to
match the line characteristic impedance. Suggested values of R2, C2 and C2’ for 80 and 160 kbit/s operation are
provided in Figures 13 and 14. Overvoltage protection is provided by R1, D1 and D2. C1 is present to properly bias
the received line signal for the L
IN
input. A 2:1 coupling transformer is used to couple to the line with a secondary
center tap for optional phantom power feed. Varistors have been shown for surge protection against such things as
lightning strikes.
If the scramblers power up with all zeros in them, they are not capable of randomizing all-zeros data sequence. This
increases the correlation between the transmit and receive data which may cause loss of convergence in the echo
canceller and high bit error rates.
In DN mode the insertion of the SYNC pattern will provide enough pseudo-random activity to maintain
convergence. In MOD mode the SYNC pattern is not inserted. For this reason, at least on ”1” must be fed into the
DNIC on power up to ensure that the scramblers will randomize any subsequent all-zeros sequence.
Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s
F0
L
OUT
SYNC
HK0
D
1
D
0
B
1
0
B
1
1
B
1
2
B
1
3
B
1
4
B
1
5
B
1
6
B
1
7
B
2
0
B
2
1
B
2
2
B
2
3
B
2
4
B
2
5
B
2
6
B
2
7
SYNC
DV Port ST-BUS
CD Port ST-BUS
Master Clocks
Mode Select
Lines
{
{
{
+5 V
0.33
μ
F
0.33
μ
F
DSTi
DSTo
CDSTi
CDSTo
F0
C4
MS0
MS1
MS2
V
Ref
V
Bias
L
OUT
L
IN
OSC1
OSC2
F0o
NC
D.C. coupled,
Frequency locked
10.24 MHz clock.
Refer to AC Electrical
R2 = 390
R1 = 47
C2’ = 1.5 nF
C2 = 22 nF
+5V
D1 = D2 = MUR405
D2
2 : 1
1.0
μ
F
Line Feed
Voltage
For 80 kbit/s: C2’ = 3.3 nF
C1 = 0.33
μ
F
68 Volts
(Typ)
2.5 Joules
0.02 Watt
Note:
Low leakage diodes (1 & 2) are required so
that the DC voltage at L
IN
≈
V
Bias
To Next DNIC
MT9171/72
Characteristics
Clock Timing
DN Mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9171 | ISO2-CMOS ST-BUS FAMILY |
| MT9171AE | ISO2-CMOS ST-BUS FAMILY |
| MT9171AN | ISO2-CMOS ST-BUS FAMILY |
| MT9171AP | ISO2-CMOS ST-BUS FAMILY |
| MT9171 | ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9171AN | 制造商:Microsemi Corporation 功能描述: |
| MT9171AN1 | 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DNIC 1.5UM - Rail/Tube |
| MT9171ANR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Subscriber Interface Circuit Digital Network Interface Circuit |
| MT9171ANR1 | 制造商:Microsemi Corporation 功能描述:PB FREE DNIC 1.5MM - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE DNIC 1.5MM - Tape and Reel |
| MT9171AP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:ISO2-CMOS ST-BUS FAMILY |
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