參數(shù)資料
型號： MT90823
廠商： Mitel Networks Corporation
英文描述： 3V Large Digital Switch(3V 大數(shù)字開關(guān))
中文描述： 3V的大型數(shù)字交換機（3V的大數(shù)字開關(guān)）
文件頁數(shù)： 5/37頁
文件大?。?/td> 162K
代理商： MT90823
CMOS
MT90823
5
36
9
6
M4
TCK
Test Clock (5V Tolerant Input):
Provides the clock to
the JTAG test logic.
37
10
7
N4
TRST
Test Reset (3.3V Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should
be pulsed low on power-up, or held low, to ensure that
the MT90823 is in the normal functional mode.
38
11
8
M5
IC
Internal Connection (3.3V Input with internal
pull-down):
Connect to V
SS
for normal operation. This
pin must be low for the MT90823 to function normally
and to comply with IEEE 1149 (JTAG) boundary scan
requirements.
39
12
9
N5
RESET
Device Reset (5V Tolerant Input):
This input (active
LOW) puts the MT90823 in its reset state to clear the
device internal counters, registers and bring STo0 - 15
and microport data outputs to a high impedance state.
The time constant for a power up reset circuit must be a
minimum of five times the rise time of the power supply.
In normal operation, the RESET pin must be held low
for a minimum of 100nsec to reset the device.
40
13
10
M6
WFPS
Wide Frame Pulse Select (5V Tolerant Input):
When
1, enables the wide frame pulse (WFP) Frame
Alignment interface. When 0, the device operates in
ST-BUS/GCI mode.
41 -
48
14-21
11 -
18
N6,M7,N7,N8,
M8,N9,M9,N10
A0 - A7
Address 0 - 7 (5V Tolerant Input):
When
non-multiplexed CPU bus operation is selected, these
lines provide the A0 - A7 address lines to the internal
memories.
49
22
19
N11
DS/RD
Data Strobe / Read (5V Tolerant Input):
For Motorola
multiplexed bus operation, this input is DS. This active
high DS input works in conjunction with CS to enable
the read and write operations.
For Motorola non-multiplexed CPU bus operation, this
input is DS. This active low input works in conjunction
with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This
active low input sets the data bus lines (AD0-AD7,
D8-D15) as outputs.
50
23
20
M10
R/W / WR
Read/Write / Write (5V Tolerant Input):
In the cases
of Motorola non-multiplexed and multiplexed bus
operations, this input is R/W. This input controls the
direction of the data bus lines (AD0 - AD7, D8-D15)
during a microprocessor access.
For multiplexed bus operation, this input is WR. This
active low input is used with RD to control the data bus
(AD0 - 7) lines as inputs.
Pin Description (continued)
Pin #
Name
Description
84
PLCC
100
MQFP
100
LQFP
120
BGA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90823AB 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 3.3V 100LQFP - Trays 制造商:Microsemi Corporation 功能描述:3V LARGE DIGITAL SWITCH
MT90823AB1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 3.3V 100LQFP - Trays 制造商:Microsemi Corporation 功能描述:3V LARGE DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 2048X2048 100LQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 2048X2048 100LQFP
MT90823AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 3.3V 120BGA - Trays
MT90823AG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 3.3V 120BGA - Trays
MT90823AL 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 3.3V 100MQFP - Trays
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