參數(shù)資料
型號(hào)： MT9045
廠商： Mitel Networks Corporation
英文描述： T1/E1/OC3 System Synchronizer(T1/E1/OC3 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）)
中文描述： T1/E1/OC3系統(tǒng)同步器（T1/E1/OC3系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成））
文件頁(yè)數(shù)： 8/25頁(yè)
文件大?。?/td> 104K
代理商： MT9045
MT9045
Advance Information
8
The active reference input (PRI or SEC) is selected
by the RSEL pin as shown in Table 2. Refer to Table
4 and Figure 7 for details of the state change
sequences.
Normal Mode
Normal Mode is typically used when a slave clock
source, synchronized to the network is required.
In Normal Mode, the MT9045 provides timing (C1.5o,
C2o,
C4o,
C8o,
C16o
synchronization (F0o, F8o, F16o, TSP and RSP)
signals, which are synchronized to one of two
reference inputs (PRI or SEC). The input reference
signal may have a nominal frequency of 8kHz,
1.544MHz, 2.048MHz or 19.44MHz.
and
C19o)
and
frame
From a reset condition, the MT9045 will take up to 30
seconds (see AC Electrical Characteristics) of input
reference
signal
to
output
synchronized (phase locked) to the reference input.
signals
which
are
The
dependent as shown in state Table 4. The reference
frequencies are selected by the frequency control
pins FS2 and FS1 as shown in Table 1.
selection
of
input
references
is
control
Fast Lock Mode
Fast Lock Mode is a submode of Normal Mode, it is
used to allow the MT9045 to lock to a reference more
quickly than Normal Mode will allow. Typically, the
PLL will lock to the incoming reference within 500ms
if the FLOCK pin is set high.
Holdover Mode
Holdover Mode is typically used for short durations
(e.g., 2 seconds) while network synchronization is
temporarily disrupted.
In Holdover Mode, the MT9045 provides timing and
synchronization signals, which are not locked to an
external reference signal, but are based on storage
techniques. The storage value is determined while
the device is in Normal Mode and locked to an
external reference signal
When in Normal Mode, and locked to the input
reference signal, a numerical value corresponding to
the MT9045 output reference frequency is stored
alternately in two memory locations every 30ms.
When the device is switched into Holdover Mode, the
value in memory from between 30ms and 60ms is
used to set the output frequency of the device.
The
±
0.05ppm, which translates to a worst case 35
frame (125us) slips in 24 hours. This satisfies the
AT&T
TR62411
and
Bellcore
Stratum 3 requirement of
±
0.37ppm (255 frame slips
per 24 hours).
frequency
accuracy
of
Holdover
Mode
is
GR-1244-CORE
Two factors affect the accuracy of Holdover Mode.
One is drift on the Master Clock while in Holdover
Mode, drift on the Master Clock directly affects the
Holdover Mode accuracy. Note that the absolute
Master Clock (OSCi) accuracy does not affect
Holdover
accuracy,
only
accuracy while in Holdover. For example, a
±
32ppm
master clock may have a temperature coefficient of
±
0.1ppm per degree C. So a
±
10 degree change in
temperature, while the MT9045 is in Holdover Mode
may
result
in
an
additional
±
0.05ppm) in frequency accuracy of
±
1ppm. Which
is much greater than the
±
0.05ppm of the MT9045.
the
change
in
OSCi
offset
(over
the
The other factor affecting accuracy is large jitter on
the reference input prior (30ms to 60ms) to the mode
switch. For instance, jitter of 7.5UI at 700Hz may
reduce the Holdover Mode accuracy from
±
0.05ppm
to
±
0.10ppm.
Freerun Mode
Freerun Mode is typically used when a master clock
source is required, or immediately following system
power-up
before
network
achieved.
synchronization
is
In Freerun Mode, the MT9045 provides timing and
synchronization signals which are based on the
master clock frequency (OSCi) only, and are not
synchronized to the reference signals (PRI and
SEC).
The accuracy of the output clock is equal to the
accuracy of the master clock (OSCi). So if a
±
32ppm
output clock is required, the master clock must also
be
±
32ppm. See Applications - Crystal and Clock
Oscillator sections.
MS2
MS1
Mode
0
0
NORMAL
0
1
HOLDOVER
1
0
FREERUN
1
1
Reserved
Table 3 - Operating Modes and States
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