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參數(shù)資料
| 型號(hào)： | MT9045 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1/OC3 System Synchronizer(T1/E1/OC3 系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）) |
| 中文描述： | T1/E1/OC3系統(tǒng)同步器（T1/E1/OC3系統(tǒng)同步裝置（由一個(gè)數(shù)字鎖相環(huán)組成）） |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 104K |
| 代理商： | MT9045 |
MT9045
Advance Information
4
38
RSEL
Reference Source Select (Input).
A logic low selects the PRI (primary) reference source as
the input reference signal and a logic high selects the SEC (secondary) input. The logic level
at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled
down to VSS.
39
IC
Internal Connection.
Tie low for normal operation.
40
FS2
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four
possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and
SEC inputs. See Table 1.
41
FS1
Frequency Select 1 (Input).
See pin description for FS2.
42
IC
Internal Connection.
Tie low for normal operation.
43
PRIOOR
Primary Reference Out Of Capture Range (Output).
A logic high at this pin indicates that
the Primary reference is off the nominal frequency by more than
±
17 ppm.
TDO
Test Serial Data Out (CMOS Output).
JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.
44
45
TDI
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
DD
.
Test Reset (Input).
Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state.
46
TRST
47
TCK
Test Clock (Input):
Provides the clock to the JTAG test logic. This pin is internally pulled up to
V
DD
.
Test Mode Select (Input).
JTAG signal that controls the state transitions of the TAP controller.
This pin is internally pulled up to V
DD
.
48
TMS
Pin Description (continued)
Pin #
Name
Description
Functional Description
The MT9045 is a Multitrunk System Synchronizer,
providing timing (clock) and synchronization (frame)
signals to interface circuits for T1 and E1 Primary
Rate Digital Transmission links. Figure 1 is a
functional block diagram which is described in the
following sections.
Reference Select MUX Circuit
The MT9045 accepts two simultaneous reference
input signals and operates on their falling edges.
Either the primary reference (PRI) signal or the
secondary reference (SEC) signal can be selected
as input to the TIE Corrector Circuit. The selection is
based
on
the
Control,
Selection of the device. See Table 1 and Table 4.
Mode
and
Reference
Frequency Select MUX Circuit
The MT9045 operates with one of four possible input
reference frequencies (8kHz, 1.544MHz, 2.048MHz
or 19.44MHz). The frequency select inputs (FS1 and
FS2) determine which of the
four frequencies may
be used at the reference inputs (PRI and SEC). Both
inputs must have the same frequency applied to
them. A reset (RST) must be performed after every
frequency select input change. See Table 1.
Table 1 - Input Frequency Selection
Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a
step change in phase on the input reference signals
(PRI or SEC) from causing a step change in phase at
the input of the DPLL block of Figure 1.
During reference input rearrangement, such as
during a switch from the primary reference (PRI) to
the secondary reference (SEC), a step change in
phase on the input signals will occur. A phase step at
FS2
FS1
Input Frequency
0
0
19.44MHz
0
1
8kHz
1
0
1.544MHz
1
1
2.048MHz
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