參數(shù)資料
型號: MT9045
廠商: Mitel Networks Corporation
英文描述: T1/E1/OC3 System Synchronizer(T1/E1/OC3 系統(tǒng)同步裝置(由一個數(shù)字鎖相環(huán)組成))
中文描述: T1/E1/OC3系統(tǒng)同步器(T1/E1/OC3系統(tǒng)同步裝置(由一個數(shù)字鎖相環(huán)組成))
文件頁數(shù): 7/25頁
文件大?。?/td> 104K
代理商: MT9045
Advance Information
MT9045
7
Figure 5 - Output Interface Circuit Block
Diagram
The frame pulse outputs (F0o, F8o, F16o, TSP, and
RSP) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a
common DPLL signal. Consequently, all frame pulse
and clock outputs are locked to one another for all
operating states, and are also locked to the selected
input reference in Normal Mode. See Figures 13 &
15.
All frame pulse and clock outputs have limited driving
capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL and
automatically enables the Holdover Mode (Auto-
Holdover) when the frequency of the incoming signal
is outside the Auto-Holdover capture range. (See AC
Electrical
Characteristics
includes a complete loss of incoming signal, or a
large frequency shift in the incoming signal. When
the incoming signal returns to normal, the DPLL is
returned to Normal Mode with the output signal
locked to the input signal. The holdover output signal
in the MT9045 is based on the incoming signal 30ms
minimum to 60ms prior to entering the Holdover
Mode. The amount of phase drift while in holdover is
-
Performance).
This
negligible because the Holdover Mode is very
accurate (e.g.,
±
0.05ppm).
phase delay between the input and output after
switching back to Normal Mode is preserved.
Consequently, the
State Machine Control
As shown in Figure 1, this state machine controls the
Reference Select MUX, the TIE Corrector Circuit and
the DPLL. Control is based on the logic levels at the
control inputs RSEL, MS1, MS2 and PCCi (See
Figure 6). When switching from Primary Holdover to
Primary Normal, the TIE Corrector Circuit is enabled
when PCCi = 1, and disabled when PCCi = 0.
All state machine changes occur synchronously on
the rising edge of F8o. See the Control and Mode of
Operation section for full details.
Figure 6 - Control State Machine Block Diagram
Master Clock
The MT9045 can use either a clock or crystal as the
master timing source. For recommended master
timing circuits, see the Applications - Master Clock
section.
Control and Mode of Operation
The MT9045 has three possible modes of operation,
Normal, Holdover and Freerun.
As shown in Table 3, Mode/Control Select pins MS2
and MS1 select the mode and method of control.
Tapped
Delay
Line
From
DPLL
T1 Divider
E1 Divider
16MHz
12MHz
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
Tapped
Delay
Line
Tapped
Delay
Line
Tapped
Delay
Line
DS2 Divider
12MHz
19MHz
C6o
C19o
RSEL
Input Reference
0
PRI
1
SEC
Table 2 - Input Reference Selection
MS1
MS2
To
Reference
Select MUX
To TIE
Corrector
Enable
Control
State Machine
To DPLL
State
Select
PCCi
RSEL
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