參數(shù)資料
型號： MT9045
廠商： Mitel Networks Corporation
英文描述： T1/E1/OC3 System Synchronizer(T1/E1/OC3 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）)
中文描述： T1/E1/OC3系統(tǒng)同步器（T1/E1/OC3系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成））
文件頁數(shù)： 6/25頁
文件大?。?/td> 104K
代理商： MT9045
MT9045
Advance Information
6
feedback signal to be externally selected (e.g., 8kHz,
1.544MHz, 2.048MHz or 19.44MHz).
Limiter
- the Limiter receives the error signal from
the Phase Detector and ensures that the DPLL
responds to all input transient conditions with a
maximum output phase slope of 5ns per 125us. This
is well within the maximum phase slope of 7.6ns per
125us or 81ns per 1.326ms specified by AT&T
TR62411
and
Bellcore
respectively.
GR-1244-CORE,
Loop Filter
- the Loop Filter is similar to a first order
low pass filter with a 1.9 Hz cutoff frequency for all
four
reference
frequency
1.544MHz, 2.048MHz or 19.44MHz). This filter
ensures that the jitter transfer requirements in ETS
300 011 and AT&T TR62411 are met.
selections
(8kHz,
Control Circuit
- the Control Circuit uses status and
control information from the State Machine and the
Input Impairment Circuit to set the mode of the
DPLL. The three possible modes are Normal,
Holdover and Freerun.
Digitally Controlled Oscillator (DCO)
- the DCO
receives the limited and filtered signal from the Loop
Filter,
and
based
on
corresponding
digital
synchronization method of the DCO is dependent on
the state of the MT9045.
its
value,
generates
signal.
a
output
The
In Normal Mode, the DCO provides an output signal
which is frequency and phase locked to the selected
input reference signal.
In Holdover Mode, the DCO is free running at a
frequency equal to the last (less 30ms to 60ms)
frequency the DCO was generating while in Normal
Mode.
In Freerun Mode, the DCO is free running with an
accuracy equal to the accuracy of the OSCi 20MHz
source.
Lock Indicator
- If the PLL is in frequency lock
(frequency lock means the center frequency of the
PLL is identical to the line frequency), and the input
phase offset is small enough such that no phase
slope limiting is exhibited, then the lock signal will be
set high.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output
Interface Circuit to provide the output signals shown
in Figure 5. The Output Interface Circuit uses four
Tapped Delay Lines followed by a T1 Divider Circuit,
an E1 Divider Circuit, and a DS2 Divider Circuit to
generate the required output signals.
Four tapped delay lines are used to generate
16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz
signals.
The E1 Divider Circuit uses the 16.384MHz signal to
generate four clock outputs and three frame pulse
outputs.
The
C8o,
C4o
generated by simply dividing the C16o clock by two,
four and eight respectively. These outputs have a
nominal 50% duty cycle.
and
C2o
clocks
are
The T1 Divider Circuit uses the 12.384MHz signal
to generate the C1.5o clock by dividing the internal
C12 clock by eight. This output has a nominal 50%
duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal
to generate the clock output C6o. This output has a
nominal 50% duty cycle.
Figure 4 - DPLL Block Diagram
Control
Circuit
State Select
from
Input Impairment Monitor
State Select
from
State Machine
Feedback Signal
from
Frequency Select MUX
DPLL Reference
to
Output Interface Circuit
Virtual Reference
from
TIE Corrector
Limiter
Loop Filter
Digitally
Controlled
Oscillator
Phase
Detector
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相關代理商/技術參數(shù)
參數(shù)描述
MT9045AN 制造商:Microsemi Corporation 功能描述:
MT9045AN1 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 3.3V 48SSOP - Rail/Tube 制造商:Microsemi Corporation 功能描述:T1/E1/OC3 SYSTEM SYNCHRONIZER
MT9045ANR1 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 3.3V 48SSOP - Tape and Reel 制造商:Microsemi Corporation 功能描述:iB FREE T1/E1/OC3 SYSTEM SYNCHRONIZER 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/OC3/T1 3.3V 48SSOP - Tape and Reel
MT9046 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Clock Multiplier PLL
MT9046AN 制造商:Microsemi Corporation 功能描述:
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