參數(shù)資料
型號: MT58L64L32D
廠商: Micron Technology, Inc.
英文描述: 64K x 32,3.3V I/O, Pipelined, Double-Cycle Deselect,SyncBurst SRAM(2Mb,3.3V輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)RAM)
中文描述: 64K的x 32,3.3六/ O的流水線,雙循環(huán)取消,SyncBurst的SRAM(處理器,3.3V的輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)內(nèi)存)
文件頁數(shù): 14/24頁
文件大小: 432K
代理商: MT58L64L32D
14
2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L128L18D_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, DCD SYNCBURST SRAM
I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS
(0°C
T
A
+70°C; V
DD
, V
DD
Q = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
Power Supply
Current: Operating
CONDITIONS
SYMBOL
TYP
-6
-7.5
-10
UNITS NOTES
Device selected; All inputs
V
IL
or
3
V
IH
; Cycle time
3
t
KC MIN;
V
DD
= MAX; Outputs open
Device selected; V
DD
= MAX;
ADSC#, ADSP#, GW#, BWx#, ADV#
3
V
IH
; All inputs
V
SS
+ 0.2 or
3
V
DD
- 0.2;
Cycle time
3
t
KC MIN
Device deselected; V
DD
= MAX;
All inputs
V
SS
+ 0.2 or
3
V
DD
- 0.2;
All inputs static; CLK frequency = 0
Device deselected; V
DD
= MAX;
All inputs
V
IL
or
3
V
IH
;
All inputs static; CLK frequency = 0
Device deselected; V
DD
= MAX;
ADSC#, ADSP#, GW#, BWx#, ADV#
3
V
IH
; All inputs
V
SS
+ 0.2 or
3
V
DD
- 0.2;
Cycle time
3
t
KC MIN
I
DD
100
340
280
225
mA
1, 2, 3
Power Supply
Current: Idle
I
DD
1
30
85
70
65
mA
1, 2, 3
CMOS Standby
I
SB
2
0.5
10
10
10
mA
2, 3
TTL Standby
I
SB
3
6
25
25
25
mA
2, 3
Clock Running
I
SB
4
30
85
70
65
mA
2, 3
NOTE:
1. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times and
greater output loading.
2. “ Device deselected” means device is in power-down mode as defined in the truth table. “ Device selected” means
device is active (not in power-down mode).
3. Typical values are measured at 3.3V, 25°C, and 10ns cycle time.
4. This parameter is sampled.
5. Preliminary package data.
TQFP CAPACITANCE
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
CONDITIONS
T
A
= 25°C; f = 1 MHz;
V
DD
= 3.3V
SYMBOL
C
I
C
O
C
A
C
CK
TYP
2.7
4
2.5
2.5
MAX
3.5
5
3.5
3.5
UNITS
pF
pF
pF
pF
NOTES
4
4
4
4
MAX
FBGA CAPACITANCE
DESCRIPTION
Address/Control Input Capacitance
Output Capacitance (Q)
Clock Capacitance
CONDITIONS
SYMBOL
C
I
C
O
C
CK
TYP
2.5
4
2.5
MAX
3.5
5
3.5
UNITS
pF
pF
pF
NOTES
4, 5
4, 5
4, 5
T
A
= 25°C; f = 1 MHz
相關(guān)PDF資料
PDF描述
MT58L128L18F 128K x 18, Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
MT58L128V18F 128K x 18, Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
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MT58L64L36F 64K x 36,Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
MT58L128L18P 128K x 18, Pipelined, SCD SyncBurst SRAM(2Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲器)
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