參數(shù)資料
型號(hào): MT58L128V18F
廠商: Micron Technology, Inc.
英文描述: 128K x 18, Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
中文描述: 128K的× 18,流量通過SyncBurst的SRAM(處理器,流通式同步脈沖靜態(tài)內(nèi)存)
文件頁數(shù): 1/24頁
文件大?。?/td> 459K
代理商: MT58L128V18F
1
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
2Mb SYNCBURST
SRAM
FEATURES
Fast clock and OE# access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL
WRITE
Three chip enables for simple depth expansion and
address pipelining
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed WRITE cycle
Burst control pin (interleaved or linear burst)
Automatic power-down
100-pin TQFP package
165-pin FBGA package
Low capacitive bus loading
x18, x32, and x36 versions available
OPTIONS
Timing (Access/Cycle/MHz)
6.8ns/8.0ns/125 MHz
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
Configurations
3.3V I/O
128K x 18
64K x 32
64K x 36
2.5V I/O
128K x 18
64K x 32
64K x 36
Packages
100-pin TQFP
165-pin FBGA
Operating Temperature Range
Commercial (0°C to +70°C)
MARKING
-6.8
-7.5
-8.5
-10
MT58L128L18F
MT58L64L32F
MT58L64L36F
MT58L128V18F
MT58L64V32F
MT58L64V36F
T
F
None
Part Number Example:
MT58L64L36FT-8.5*
*A Part Marking Guide for the FBGA devices can be found on Micron’s
web site—
http://www.micronsemi.com/support/index.html
.
MT58L128L18F, MT58L64L32F,
MT58L64L36F; MT58L128V18F,
MT58L64V32F, MT58L64V36F
3.3V V
DD
, 3.3V or 2.5V I/O, Flow-Through
GENERAL DESCRIPTION
The Micron
SyncBurst
SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 2Mb SyncBurst SRAMs integrate a 128K x
18, 64K x 32, or 64K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
100-Pin TQFP*
165-Pin FBGA
(Preliminary Package Data)
*JEDEC-standard MS-026 BHA (LQFP).
相關(guān)PDF資料
PDF描述
MT58L64L32F 64K x 32,Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
MT58L64L36F 64K x 36,Flow-Through SyncBurst SRAM(2Mb,流通式同步脈沖靜態(tài)RAM)
MT58L128L18P 128K x 18, Pipelined, SCD SyncBurst SRAM(2Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128V18P 128K x 18, Pipelined, SCD SyncBurst SRAM(2Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L64L32P 64K x 32,Pipelined, SCD SyncBurst SRAM(2Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
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