![](http://datasheet.mmic.net.cn/390000/MT58L64L18F_datasheet_16823638/MT58L64L18F_3.png)
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM
MT58L64L18F.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
3
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. GW#
LOW causes all bytes to be written. Parity bits are only
available on the x18 and x36 versions.
Micron’s 1Mb SyncBurst SRAMs operate from a
+3.3V power supply, and all inputs and outputs are
TTL-compatible. The device is ideally suited for 486,
Pentium
, 680X 0 and PowerPC systems and systems
that benefit from a very wide data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64- and 72-bit-wide
Please to (www.micron.com/mti/msp/html/sramprod.html
) for
the latest data sheet.
W eb TQFP PIN ASSIGNMENT TABLE